t_line - Prediction of High-Performance On-Chip Global...

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Unformatted text preview: Prediction of High-Performance On-Chip Global Interconnection Yulei Zhang 1 , Xiang Hu 1 , Alina Deutsch 2 , A. Ege Engin 3 James F. Buckwalter 1 , and Chung-Kuan Cheng 1 1 Dept. of ECE, UC San Diego, La Jolla, CA 2 IBM T. J. Watson Research Center, Yorktown Heights, NY 3 Dept. of ECE, San Diego State Univ., San Diego, CA 2 Outline Introduction Technology trend Current approaches On-Chip Global Interconnection Overview: structures, tradeoffs Interconnect schemes Global wire modeling Performance analysis Design Methodologies for T-line schemes Prediction of Performance Metrics Experimental settings Performance metrics comparison and scaling trend Latency Energy per bit Throughput Signal Integrity Conclusion 3 Introduction Performance Impact Interconnect delay determines the system performance [ITRS08] 542ps for 1mm minimum pitch Cu global wire w/o repeater @ 45nm ~ 150ps for 10 level FO4 delay @ 45nm [Ho2001] Future of Wire 4 Introduction Power Dissipation Interconnects consume a significant portion of power 1-2 order larger in magnitude compared with gates Half of the dynamic power dissipated on repeaters to minimize latency [Zhang07] Wires consume 50% of total dynamic power for a 0.13um microprocessor [Magen04] About 1/3 burned on the global wires. 5 Introduction Different Approaches and Our Contributions Different Approaches Repeater Insertion Approach Pros: High throughput density . Cons: Overhead in terms of power consumption and wiring complexity. T-line Approach [Zhang09] Pros: Low latency . Cons: low throughput density due to low bandwidth and large wire dimension Equalized T-line Approach [Zhang08] Pros: Low power, Low noise, Higher throughput than single-ended. Cons: The area overhead brought by passive components. We explore different global interconnection structures and compare their performance metrics across multiple technology nodes. Contributions: A simple linear model A general design framework A complete prediction and comparison 6 Organization of On-Chip Global Interconnections 7 Multi-Dimensional Design Consideration Preliminary analysis results assuming 65nm CMOS process. Application-oriented choice Low Latency T-TL T-TL or or UT-TL UT-TL -> Single-Ended T-lines-> Single-Ended T-lines High Throughput R-RC R-RC Low Power PE-TL PE-TL or or UE-TL UE-TL Low Noise PE-TL PE-TL or or UE-TL UE-TL Low Area/Cost R-RC R-RC Differential T-lines Differential T-lines For each architecture, the more area the pentagon covers, the better overall performance is achieved. 8 On-Chip Global Interconnect Schemes (1) Repeated RC wires (R- RC) Un-Terminated Un-Terminated and and Terminated T-Line Terminated T-Line ( UT-TL UT-TL and and T-TL T-TL ) R-RC structure Repeater size/Length of segments Adopt previous design methodology [Zhang07]...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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t_line - Prediction of High-Performance On-Chip Global...

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