Lecture 3 Concurrency

Lecture 3 Concurrency - Review: Thread package API tid...

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Unformatted text preview: Review: Thread package API tid thread create (void (*fn) (void *), void *arg);- Create a new thread that calls fn with arg void thread exit (); void thread join (tid thread); The execution of multiple threads is interleaved Can have non-preemptive threads :- One thread executes exclusively until it makes a blocking call. Or preemptive threads :- May switch to another thread between any two instructions. Using multiple CPUs is inherently preemptive- Even if you dont take CPU away from thread T , another thread on CPU 1 can execute between any two instructions of T . 1/39 Program A int flag1 = 0, flag2 = 0; void p1 (void *ignored) { flag1 = 1; if (!flag2) { critical_section_1 (); } } void p2 (void *ignored) { flag2 = 1; if (!flag1) { critical_section_2 (); } } int main () { tid id = thread_create (p1, NULL); p2 (); thread_join (id); } Can both critical sections run? 2/39 Program B int data = 0, ready = 0; void p1 (void *ignored) { data = 2000; ready = 1; } void p2 (void *ignored) { while (!ready) ; use (data); } int main () { ... } Can use be called with value 0? 3/39 Program C int a = 0, b = 0; void p1 (void *ignored) { a = 1; } void p2 (void *ignored) { if (a == 1) b = 1; } void p3 (void *ignored) { if (b == 1) use (a); } int main () { ... } Can use be called with value 0? 4/39 Correct answers Program A: I dont know Program B: I dont know Program C: I dont know Why?- It depends on your hardware- If it provides sequential consistency , then answers all No- But not all hardware provides sequential consistency Note: Examples and other slide content from [Adve & Gharachorloo] 5/39 Sequential Consistency Sequential consistency : The result of execution is as if all operations were executed in some sequential order, and the operations of each processor occurred in the order specified by the program. [Lamport] Boils down to two requirements: 1. Maintaining program order on individual processors 2. Ensuring write atomicity Without SC, multiple CPUs can be worse than preemptive threads- May see results that cannot occur with any interleaving on 1 CPU Why doesnt all hardware support sequential consistency? 6/39 SC thwarts hardware optimizations Complicates write buffers- E.g., read flag n before flag ( 2- n ) written through in Program A Cant re-order overlapping write operations- Concurrent writes to different memory modules- Coalescing writes to same cache line Complicates non-blocking reads- E.g., speculatively prefetch data in Program B Makes cache coherence more expensive- Must delay write completion until invalidation/update ( Program B )- Cant allow overlapping updates if no globally visible order ( Program C ) 7/39 SC thwarts compiler optimizations Code motion Caching value in register- E.g., ready flag in Program B Common subexpression elimination- Could cause memory location to be read fewer times Loop blocking- Re-arrange loops for better cache performance...
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This note was uploaded on 03/13/2010 for the course CS 02523 taught by Professor Davidmieres during the Winter '10 term at A.T. Still University.

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Lecture 3 Concurrency - Review: Thread package API tid...

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