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Lecture 6 Synchronization

Lecture 6 Synchronization - Administrivia Project 1 due...

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Administrivia Project 1 due right now - Free extension if you are here - Of for SCPD students who watch lecture before midnight To get extension - Put “ ” at top of your design document Project 2 section tomorrow 3:15pm here I will be out of town Monday - Will hold office hours Wednesday, 2:30pm instead 1/41
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Readers-Writers Problem Multiple threads may access data - Readers – will only observe, not modify data - Writers – will change the data Goal: allow multiple readers or one single writer - Thus, lock can be shared amongst concurrent readers Can implement with other primitives - Keep integer i – # or readers or -1 if held by writer - Protect i with mutex - Sleep on condition variable when can’t get lock 2/41
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Implementing shared locks struct sharedlk { int i; mutex_t m; cond_t c; }; void AcquireExclusive (sharedlk *sl) { lock (sl->m); while (sl->i) { wait (sl->m, sl->c); } sl->i = -1; unlock (sl->m); } void AcquireShared (sharedlk *sl) { lock (sl->m); while (sl->i < 0) { wait (sl->m, sl->c); } sl->i++; unlock (sl->m); } 3/41
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shared locks (continued) void ReleaseShared (sharedlk *sl) { lock (sl->m); if (!--sl->i) signal (sl->c); unlock (sl->m); } void ReleaseExclusive (sharedlk *sl) { lock (sl->m); sl->i = 0; broadcast (sl->c); unlock (sl->m); } Note: Must deal with starvation 4/41
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Review: Test-and-set spinlock struct var { int lock; int val; }; void atomic_inc (var *v) { while (test_and_set (&v->lock)) ; v->val++; v->lock = 0; } void atomic_dec (var *v) { while (test_and_set (&v->lock)) ; v->val--; v->lock = 0; } 5/41
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Relaxed consistency model Suppose no sequential consistency Recall alpha mb (mem. barrier)—what if we omit it? - Hardware could violate program order PROGRAM ORDER VIEW ON OTHER CPU read/write: v->lock = 1; v->lock = 1; read: v->val; write: v->val = read val + 1; write: v->lock = 0; v->lock = 0; /* danger */ v->val = read_val + 1; If atomic dec called where danger , bad val results mb in test and set preserves program order - All ops before mb in program order appear before on all CPUs - All ops after mb in program order appear after on all CPUs Many example in this lecture assume S.C. - Need to add barrier instructions on non-S.C. hardware 6/41
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Cache coherence Performance requires caches Sequential consistency requires cache coherence Barrier & atomic ops require cache coherence Bus-based approaches - “Snoopy” protocols, each CPU listens to memory bus - Use write through and invalidate when you see a write - Or have ownership scheme (e.g., Pentium MESI bits) - Bus-based schemes limit scalability Cache-Only Memory Architecture (COMA) - Each CPU has local RAM, treated as cache - Cache lines migrate around based on access - Data lives only in cache 7/41
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cc-NUMA Previous slide had dance hall architectures - Any CPU can “dance with” any memory equally An alternative: Non-Uniform Memory Access - Each CPU has fast access to some “close” memory - Slower to access memory that is farther away - Use a directory to keep track of who is caching what Originally for machines with many CPUs - Now AMD Opterons are kind of like this - Next generation Intel CPUs will be like this, too cc-NUMA = cache-coherent NUMA - Can also have non-cache-coherent NUMA, though uncommon - BBN Butterfly 1 has no cache at all - Cray T3D has local/global memory 8/41
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