Lecture 11 IO and disks

Lecture 11 IO and disks - Midterm 2 4 6 8 10 12 20 40 60 80...

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Unformatted text preview: Midterm 2 4 6 8 10 12 20 40 60 80 100 "midterm.data" using 1:2 1/37 Questions on Midterm • Problems 1–2: See David • Problem 3: See Jeremy or Samir • Problem 4: See Jeremy • Problem 5: See Jeff • Problem 6: See Andrew • Problem 7: See Samir 2/37 Administrivia • Recall we will have a resurrection final- Don’t panic if you didn’t do well on midterm- But make sure you understand all the answers- There may be questions on same topics on the final • Final grade based on rank and thresholds- Rank based on Projects + max ( Final,Midterm + Final/2 )- Letter grade thresholds (“curve”) more influenced by projects • Recall: Project 3 section tomorrow 3/37 Memory and I/O buses I/O bus 1880Mbps 1056Mbps Crossbar Memory CPU • CPU accesses physical memory over a bus • Devices access memory over I/O bus with DMA • Devices can appear to be a region of memory 4/37 Realistic PC architecture Advanced Programable Interrupt Controller bus I/O APIC CPU Bridge Main memory North bus side front- South Bridge bus ISA CPU USB bus AGP PCI IRQs bus PCI 5/37 What is memory? • SRAM – Static RAM- Like two NOT gates circularly wired input-to-output- 4–6 transistors per bit, actively holds its value- Very fast, used to cache slower memory • DRAM – Dynamic RAM- A capacitor + gate, holds charge to indicate bit value- 1 transistor per bit – extremely dense storage- Charge leaks—need slow comparator to decide if bit 1 or 0- Must re-write charge after reading, and periodically refresh • VRAM – “Video RAM”- Dual ported, can write while someone else reads 6/37 What is I/O bus? E.g., PCI 7/37 Communicating with a device • Memory-mapped device registers- Certain physical addresses correspond to device registers- Load/store gets status/sends instructions – not real memory • Device memory – device may have memory OS can write to directly on other side of I/O bus • Special I/O instructions- Some CPUs (e.g., x86) have special I/O instructions- Like load & store, but asserts special I/O pin on CPU- OS can allow user-mode access to I/O ports with finer granularity than page • DMA – place instructions to card in main memory- Typically then need to “poke” card by writing to register- Overlaps unrelated computation with moving data over (typically slower than memory) I/O bus 8/37 DMA buffers Buffer descriptor list Memory buffers 100 1400 1500 1500 1500 … • Include list of buffer locations in main memory • Card reads list then accesses buffers (w. DMA)- Descriptions sometimes allow for scatter/gather I/O 9/37 Example: Network Interface Card Host I/O bus Adaptor Network link Bus interface Link interface • Link interface talks to wire/fiber/antenna- Typically does framing, link-layer CRC • FIFOs on card provide small amount of buffering • Bus interface logic uses DMA to move packets to and from buffers in main memory 10/37 Example: IDE disk read w. DMA 11/37 Driver architecture • Device driver provides several entry points to kernel...
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Lecture 11 IO and disks - Midterm 2 4 6 8 10 12 20 40 60 80...

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