2 - I nstr uction set Summar y I nstr uction For mats Oper...

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Unformatted text preview: I nstr uction set Summar y I nstr uction For mats Oper ations Addr essing M odes Pr ogr ammer s Register s CONTROL LOGI C UNI T- Dir ects all har dwar e activity inside- Contr ols Fetch, Decode, Execute Cycle M acr o/M icr o I nstr uctions Example M icr oinstr uctions : Open/.Close a gate fr om Reg to a bus Tr ansfer data along a bus Send timing signals Test bits within a r egister I nstruction Decoder I R PC MAR MDR R0 Rn-1 Y ALU Z Address Bus Data Bus CPU Bus A B Control Lines Clear Y CPU Oper ations Fetch a wor d fr om M emor y Stor e a wor d into memor y Reg Tr ansfer s Per for ming an ALU function Fetching a wor d fr om memor y : i. M AR ← (R1) ii. Read Signal iii. Wait for M emor y-function- complete (M FC) signal iv. R2 ← (M DR) Stor ing a wor d into M emor y: i. M AR ← (R1) ii. M DR ← (R2) iii. M emor y wr ite signal iv. Wait for M FC Register Transfers: R2 ← R1 To enable data transfer between various Blocks connected to common bus provide I nput output gating. R Ri n Rou t ALU Y Z Zout Zin Yin Per for ming an Ar ithmetic or Logic Oper ation : i. R1 out , Y in ii. R2 out , Add, Z in iii. Z out , R3 in Step...
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This note was uploaded on 03/14/2010 for the course CSE SSZG516 taught by Professor Muralip during the Summer '10 term at Birla Institute of Technology & Science.

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2 - I nstr uction set Summar y I nstr uction For mats Oper...

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