NgLoo - An Improved Error Recovery Mechanism to the Razor...

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An Improved Error Recovery Mechanism to the Razor Pipeline Architecture Timothy Loo Vincent Ng University of California, Berkeley 1. Introduction After decades of astonishing improvement in integrated circuit performance, digital circuits have come to a point in which there are many problems ahead of us. Two main problems are power consumption and process variations. In the past few decades, circuit designs have followed Moore’s law and the number of transistors on a chip has doubled every two years. As we fit more transistors into a given area and clocked them faster and faster, power density increases exponentially. The most effective way to reduce power density is to minimize the supply voltage, as predicted by CV 2 f. Currently, we have been successful in containing the power density within tolerable levels, but this will not last. One barrier comes from the threshold voltage. In order to maintain the same performance, we have to reduce the threshold voltage together with the supply voltage. However, reducing threshold voltage leads to an exponential increase in off-state leakage current. Leakage current has become so significant that a further reduction in threshold voltage and supply voltage has slowed or even stopped. Without voltage scaling, the power density of a chip will increase without bound. A temperature on a processor already approaches that of a hot plate, and this trend cannot be allowed it to continue. If a solution to this ever increasing power consumption cannot be found, Moore’s law will come to an end and we will no longer be able to experience the tremendous increase in performance experienced in the past. The other problem of the IC industry is process variations. As transistor sizes approach atomic levels, it is very difficult to fabricate exactly what we specify. For example, a variation of dopant implantation on order of a few atoms may translate to a huge difference in dopant concentration, and may cause a noticeable shift in the threshold voltage. Because traditional designs dictate that our circuit must always function correctly in all circumstances, the huge process variations present today forces designers to allocate more voltage margin on top of the typical case in order to ensure proper operation. To make things worse, other temperature, die-to-die, and IR drop variations further increases safety margins needed. The general practice of conservative over design has become a barrier to low power design. Because these large margins are used only to prevent the rare worst case scenario from failing, a large amount of energy can be saved if these margins are eliminated and instead utilize an error-resilient logic that can dynamically tune itself for all kinds of variations. We will then be able to run our chip at the lowest possible energy consumption. Power consumption and variations have
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NgLoo - An Improved Error Recovery Mechanism to the Razor...

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