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lab2assignment

lab2assignment - CSE140L Spring...

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CSE 140L Spring 2008:  Announcements  |  Syllabus  |  Schedule  |  Materials CSE 140L Spring 2008 Lab 2 Assignment Demo due on May. 11, 10pm,  Report due on May. 12, 12pm. Objective - Learn how to use Verilog design flow in ISE. - Learn how to design basic sequential circuits - Understand the effect of gate delay upon circuit function. Part 1. Introductory Tutorial Here is a step-by-step HDL(Hardware Description Language) flow in ISE. Most steps are the same  with schematic flow except that the source is verilog file (.v) in this flow. Step by step example of Verilog design flow in ISE9.2i Part 2. Tic-Tac-Toe game  We borrow this game from Stanford EE 108A, and you need to expand the given Tic-Tac-Toe 
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module to have more functionality.  Please read the class notes (Chapter 9.4) very carefully:  class notes . It gives very good explanations of the modeling of the game. If you don’t understand it, it would be  very hard to do this part. Also, in this part, we use the VGA output of the board. In our lab, there should be a switch box that  can switch the LCD between PC VGA output and board VGA output. The original version Tic-Tac-Toe game has been implemented and is available at  starter file . (Don’t  use the starter file from Stanford website, since we modified the inputs) To get this version work: 1. Unzip the starter files into some folder. You should see a bunch of verilog files, and a ucf file. 2. Open ISE navigator and build a new project, set the top-level source type as HDL, and set the  hardware property the same as before.  3. When asked to add sources, you need to add all the verilog files into your project. 4. Once the project has been built, you should see all these verilog files appear in the source  window, and the top module is tictactoe_top.v 5. Generate a test bench waveform with the following waveforms(The only thing you need to  change from default is the total simulation time, set it as 10000ns): 
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6. Run functional simulation on the testbench. From the simulation results, you should be able to interpret how the inputs work together.  Don’t look those vga_*** outputs, they are normally X. You need to check new_x_d, new_o_d,  current_x_q, current_o_q, next_x_d and make you understand their values.
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