lab1assignment

lab1assignment - CSE140L Spring...

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CSE 140L Spring 2008:  Announcements  |  Syllabus  |  Schedule  |  Materials CSE 140L Spring 2008 Lab 1 Assignment Due on Apr. 23 Objective - Get familiar with the XUP Virtex-II Pro board and the ISE webpack tool. - Learn how to design basic combinational digital components.  - Learn how to download designs onto the FPGA platform.  - Learn how to do functional and timing simulations and to examine the resulting waveforms. Please note: For this lab assignment, most design work includes the following steps: 1. Schematic design 2. Functional simulation 3. Pin assignment 4. Downloading design to FPGA For the steps of 1 and 2, you can work without XUP board and just use ISE webpack only, which  means you can do it on your own PC. Once you have verified the correctness of your design, just save your project files, copy your  project folder to some portable devices or upload it somewhere online.
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Then you can come to lab, copy your files into PCs in the lab, and complete steps 3 and 4 using  ISE. In this way, we can alleviate the resource pressure in our lab. Part 1. Introductory Tutorial Please read carefully and follow along with these tutorials. Make sure you understand each step. The content covered in the tutorials is the very basics for designing and simulating circuits with hw/ sw platform. If you have any questions when following the tutorials, please ask TA for help. Simple hardware tutorial Step by step example of schematic flow design with ISE9.2i Report Write a short report (max 200 words) of the overall process of using ISE9.2i to design a simple  combinatorial circuit, and making it work correctly with your board.
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