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lab_wk1 - CSE140L: Components and Design Techniques for...

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SE140L: Components and Design CSE140L: Techniques for Digital Systems Lab Introduction Tajana Simunic Rosing 1
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Welcome to CSE 140L! Course time: W 2-2:50pm, WLH 2205 iscussion session: 12 2:50pm SE 3219 Discussion session: F 12-12:50pm, CSE 3219 Instructor: Tajana Simunic Rosing • Email: tajana@ucsd.edu ; please put CSE140L in the subject line • Ph. 858 534-4868 ffice Hours: u h pm SE 2118 Office Hours: Tu/Th 1-2pm, CSE 2118 Instructor’s Assistant: Sheila Manalo – Email: shmanalo@ucsd.edu – Phone: (858) 534-8873 A: Ling Zhang TA: Ling Zhang – Email: lizhang@cs.ucsd.edu – Office hours: M 2-3pm; W 10-11am in CSE 3219 TA: Chun Chen Liu mail: hl084@ucsd edu Email: chl084@ucsd.edu – Office hours: T 10am-12pm in CSE 3219 Class Website: http://www.cse.ucsd.edu/classes/sp08/cse140L/ rades: ttp://webct ucsd edu 2 Grades: http://webct.ucsd.edu
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Course Description • Prerequisites: – CSE 20 or Math 15A, and CSE 30. – CSE 140 must be taken concurrently • Objective: troduce digital components and system design concepts through Introduce digital components and system design concepts through hands-on experience in a lab • Grading abs (4): 70% Labs (4): 70% • We have 15 Xilinx platforms with PCs – organize in teams of two • Schedule for lab access; need to schedule a demo to TA by lab due date • Go to Robin Knox [rsknox@cs.ucsd.edu] office in CSE 2248 to program our student ID for access to CSE 3219 your student ID for access to CSE 3219 – Monday-Thursday 10-12:30 and 2:00-4:00 – Final exam: 30% – Regrade requests: turn in a written request at the end of the class 3 where your work is returned
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Textbook and Recommended Readings Required textbook: ontemporary Logic Design by Contemporary Logic Design by R. Katz & G. Borriello Recommended textbook: – Digital Design by F. Vahid Lecture slides are derived from the 4 slides designed for both books
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Hardware we will use Freely available in CSE 3219 lab: ilinx irtex Pro Development System Xilinx Virtex-II Pro Development System (XUPV2P) http://www.xilinx.com/univ/xupv2p.html C in the lab already have ISE tools installed PC in the lab already have ISE tools installed. You can program boards in the lab only! You can download on your own PC Webpack implement and test your design before to implement and test your design before programming the board www.xilinx.com/ise/logic_design_prod/webpack.htm Alternative: Altera Board you can buy in the bookstore for $100 5
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Outline • Introduction to Xilinx board & tools • Transistors – How they work – How to build basic gates out of transistors ow to evaluate delay How to evaluate delay • Pass gates • Muxes 6
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Basic FPGA Architecture
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Overview • All Xilinx FPGAs contain the same basic sources resources – Slices grouped into configurable logic blocks - CLBs • Contain combinatorial logic and register resources – Input/Output Blocks - IOBs • Interface between the FPGA and the outside world – Programmable interconnect – Other resources rocessor Processor • Memory • Multipliers • Global clock buffers • Boundary scan logic
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This note was uploaded on 03/16/2010 for the course CSE 140 taught by Professor Rosing during the Winter '06 term at UCSD.

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lab_wk1 - CSE140L: Components and Design Techniques for...

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