lab_wk2

lab_wk2 - CSE140L: Components and Design Techniques for...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
SE140L: Components and Design CSE140L: Techniques for Digital Systems Lab Timing, Mux, Demux, Adders Tajana Simunic Rosing 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Outline • Non-ideal gate behavior (3.5) – Rise/fall time – Delay – Pulse width • Pass gates (Appendix B) g( p p ) • Muxes & Demuxes (chap 4.2 pp. 171-183) • Adders (chap 5.6) 2
Background image of page 2
Charge/discharge in CMOS • Calculate on resistance alculate capacitance of the gates circuit is driving Calculate capacitance of the gates circuit is driving • Get RC delay & use it as an estimate of circuit delay –V out = V dd ( 1- e -t/RpC ) 3 Source: Prof. Subhashish Mitra
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Time behavior of combinational networks Waveforms visualization of values carried on signal wires over time – useful in explaining sequences of events (changes in value) Simulation tools are used to create these waveforms put to the simulator includes gates and their connections input to the simulator includes gates and their connections – input stimulus, that is, input signal waveforms Some terms ate delay me for change at input to cause change at output gate delay — time for change at input to cause change at output • min delay – typical/nominal delay – max delay • careful designers design for the worst case rise time — time for output to transition from low to high voltage pg g – fall time — time for output to transition from high to low voltage – pulse width — time that an output stays high or stays low between changes
Background image of page 4
Non-Ideal Gate Behavior – Delay a F F a Time • Real gates don’t respond immediately to input changes – Rise/fall time elay 5 – Delay – Pulse width
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Waveform view of logic functions • Just a sideways truth table – but note how edges don’t line up exactly me – it takes time for a gate to switch its output! time 6 change in Y takes time to "propagate" through gates
Background image of page 6
Momentary changes in outputs • Can be useful — pulse shaping circuits an be a problem correct circuit operation AB C D Can be a problem incorrect circuit operation (glitches/hazards) • Example: pulse shaping circuit F –A A = 0 – delays matter remains high for 7
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/16/2010 for the course CSE 140 taught by Professor Rosing during the Winter '06 term at UCSD.

Page1 / 29

lab_wk2 - CSE140L: Components and Design Techniques for...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online