lecture3

lecture3 - Two-level Combinational Circuit Z. Jerry Shi...

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1 Two-level Combinational Circuit Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE2300W:Digital Logic Design Brute-force design •T r u t h t a b l e Æ Canonical sum (Sum of minterms) • Example: Design a circuit to detect prime numbers between 0-15 Given a 4-bit input, N 3 N 2 N 1 N 0 , produce a 1 output for N = 1, 2, 3, 5, 7, 11, 13 and a 0 otherwise row N 3 N 2 N 1 N 0 F 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 0 0 1 1 1 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 1 0 F = Σ N3, N2, N1, N0 (1,2,3,5,7,11,13)
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2 Minterm list Æ Canonical sum Algebraic simplification • Theorem T10: X • Y + X • Y ' = X • Reduce number of gates and gate inputs
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3 Resulting circuit Sum-of-products Form AND-OR NAND-NAND
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4 Product-of-sums form OR-AND NOR-NOR Sum-of-products preferred in CMOS and TTL (NAND-NAND) Circuit minimization All the logic functions can be implemented with two level logic networks – Canonical sum and canonical product – Become intractable when there are a lot of inputs Minimize circuit : reduce the cost to build the circuit while satisfying all the constraints – Constraints: time (delay), area, power, etc. – Cost: area, time to market, etc. The minimization method we will study reduces the cost of two-level AND- OR, OR-AND. NAND-NAND, NOR-NOR circuit – Minimizing the number of first-level gates – Minimizing the number of inputs on each first-level gates – Minimizing the number of inputs on the second-level gate We assume the true and complemented forms of input signals are available
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5 Karnaugh Map Visualizing T10 -- Karnaugh maps (1) T10: X • Y + X • Y ' = X Adjacent cells can be merged (reduced) Minterm5:± ±W± '•X±•Y± '•Z Minterm13: ±W±•X ±•Y± X • Y ' • Z 11
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6 Visualizing T10 -- Karnaugh maps (2) T10: X • Y + X • Y ' = X Minterm1:±±W± '•X± '•Y± '•Z Minterm9:± ±W±•X± X ' • Y ' • Z 11 Visualizing T10 -- Karnaugh maps (3) Minterm 5 and Minterm 13: X • Y ' • Z Minterm 1 and Minterm 9: X ' • Y ' • Z Y ' • Z Each mergence removes one literal 2 i cells Æ ( n i ) literals Corresponding product terms: covers only 1: variables covers only 0: complement of variables covers both 0 and 1: not included
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7 Merging cells Example: F = Σ (1,2,5,7)
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8 Karnaugh-map usage Plot 1’s corresponding to minterms of function Circle largest possible rectangular sets of 1’s – Number of 1’s in a set must be power of 2 – OK to cross edges Read off product terms, one per circled set – Variable is 1 ==> include variable – Variable is 0 ==> include complement of variable – Variable is both 0 and 1 ==> variable not included
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This note was uploaded on 03/16/2010 for the course CSE 2300W taught by Professor Shi during the Fall '08 term at UConn.

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lecture3 - Two-level Combinational Circuit Z. Jerry Shi...

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