lecture6_seq

lecture6_seq - Sequential Circuits Z Jerry Shi Computer...

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1 Sequential Circuits Z. Jerry Shi Computer Science and Engineering University of Connecticut Thank John Wakerly for providing his slides and figures. Sequential circuits • Output depends on current input and past history of inputs • “State” embodies all the information about the past needed to predict current output based on current input. State variables , one or more bits of information – “Memory” to remember state between two inputs
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2 Clock signals • Very important with most sequential circuits – State variables change state at clock edge. Bistable element • The simplest sequential circuit • Two states – One state variable, say, Q HIGH LOW LOW HIGH
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3 Bistable element • The simplest sequential circuit • Two states – One state variable, say, Q LOW HIGH HIGH LOW Analog analysis • Assume pure CMOS thresholds, 5 V rail • Theoretical threshold center is 2.5 V
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4 Analog analysis • Assume pure CMOS thresholds, 5V rail • Theoretical threshold center is 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 5.0 V 4.8 V Analog analysis • Assume pure CMOS thresholds, 5V rail • Theoretical threshold center is 2.5 V 0.0 V 0.0 V
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5 Metastability • Metastability is inherent in any bistable circuit • Two stable points, one metastable point Control bistable • How to control it? – Grandpa’s screwdrivers? – Control inputs S and R • S-R latch
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6 S-R latch operation Metastability is possible if S and R are negated simultaneously. S-R latch timing parameters • Propagation delay • Minimum pulse width
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7 S-R latch symbols S-R latch using NAND gates
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8 S-R latch with enable D latch
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9 D-latch operation When C = 1, Q = D. When C = 0, Q does not change. D-latch timing parameters • When C = 1, Q follows D – Propagation delay (from C or D) • When C = 0, Q remembers D’s value at the 1 Æ 0 transition – Setup time (D before C’s falling edge) – Hold time (D after C’s falling edge)
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10 Positive edge-triggered D flip-flop ~ QM = D Enabled D Disabled D D D D D Disabled ~ D Enabled 0 1 0 CLK_L 1 0 ~ QM = D Enabled D Disabled 1 Q Latch 2 Status QM Latch 1 Status CLK 12 Positive edge-triggered D flip-flop behavior
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11 D flip-flop timing parameters • Propagation delay (from CLK) • Setup time (D before CLK) • Hold time (D after CLK) CMOS positive edge-triggered D flip-flop • Two feedback loops (master and slave latches) • Uses transmission gates in feedback loops
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12 Positive edge-triggered D flip-flop with preset and clear • Preset and clear inputs – Like S-R latch TTL positive edge-triggered D commercial circuit (x74) • Preset and clear inputs • 3 feedback loops – interesting analysis (Sec. 7.9) • Light loading on D
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13 Negative edge-trigged D flip-flop Invert the input CLK signal Positive-edge-triggered D flip-flop with enable How does EN works?
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14 Scan flip-flop How is this circuit different from the previous one?
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This note was uploaded on 03/16/2010 for the course CSE 2300W taught by Professor Shi during the Fall '08 term at UConn.

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lecture6_seq - Sequential Circuits Z Jerry Shi Computer...

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