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HW2 - Q1(15pts)(40points Loop LD R1,0(R2;loadR1=MEM[0 R2...

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CS 282 – Computer Architecture and Organization – Assignment 2 (40 points) Q1. (15 pts) Use the following code fragment: Loop: LD R1, 0(R2) ; load R1 = MEM[0+R2] DADDI R1, R1, 1 ; R1 = R1+1 SD 0(R2), R1 ; store MEM[0+R2] = R1 DADDI R2, R2, 4 ; R2 = R2+4 DSUB R4, R3, R2 ; R4 = R3 R2 BNE R4, R0, Loop ; branch to Loop if (R4 != 0) Assume that the initial value of R3 is R2 + 396. Throughout this exercise use the classic 5 stage MIPS pipeline and assume that all memory accesses take 1 clock cycle. a. (5 pts) Show the timing of this instruction sequence for the RISC pipeline without any forwarding hardware, but assuming that a register read and a write in the same clock cycle forwards through the register file. Use a pipeline timing chart, such as Figure A.5. Assume that branch is handled by flushing the pipeline and that the PC is updated at the end of the execute stage. How many clock cycles does this loop take to execute (for all iterations)? b. (5 pts) Show the timing of this instruction sequence for the RISC pipeline with normal forwarding and bypassing hardware. Assume that the branch instruction is handled by flushing
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