FET Biasing

FET Biasing - Simple FET DC Bias Circuits Bob York...

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©B ob Y o rk Simple FET DC Bias Circuits
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©B obY o rk Back to TOC Load-Line and Q-point V out I d R D V gs The points of intersection represent the allowed device voltages and drain current for the resistor-FET combination. These are the “quiescent” operating conditions or “Q points”, i.e. the DC bias conditions. There are a number of possible Q-points along the load-line, depending on the gate voltage. It is the job of the circuit designer to choose this Q-point. The choice of Q-point will vary with the circuit application. For simple amplifier circuits a Q- point in the middle of the saturation region is often desirable. Consider the effect of a drain resistor in the comnon-source configuration: V ds dd d d ds VI R V +V dd KVL: 1 dd dd s V IV RR  This is the equation of a line that can be superimposed on the FET I-V characteristics as shown at right. This is the “load-line”. V ds / dd d VR knee V Q point Larger R d dd V Smaller R d V gs = V tn + 1.0 V gs = V tn + 1.5 V gs = V tn + 2.0 Increasing V gs I d
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©B obY o rk Back to TOC FET DC Biasing V out I d R D V gs 2 () dn g s t IK VV  Consider the design of the circuit to set a certain Q-point: V ds 10V 6V 200 20mA d R  FET Parameters: 2 1V 5mA/V t n V K +10 V Design goal: 20mA out d V I The design goal puts the Q-point right in the middle of the saturation region in the I-V curves where V ds 10 V gs = 2 V gs = 3 V gs = 4 I d 6 45mA 20mA 5mA 2 3V d gs t n I K  To get a 4V drop across the drain resistor @ 20mA current requires a resistor value
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This note was uploaded on 03/17/2010 for the course ECE 2B taught by Professor York during the Winter '07 term at UCSB.

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FET Biasing - Simple FET DC Bias Circuits Bob York...

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