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Lecture_3

# Lecture_3 - CSE 331 Computer Organization and Design Spring...

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CSE331 W03.1 KB Spring 2008SP PSU CSE 331 Computer Organization and Design Spring 2010 Week 3 Section 1: Course material on ANGEL: cms.psu.edu [Thanks to M. J. Irwin versions of D. Patterson slides ]

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CSE331 W03.2 KB Spring 2008SP PSU Head’s Up CSE 331.1&2 – Exam 1 on 2/15/2010 - 6:30-7:45 p.m. - 26 Hosler EXAM 2 - 3/31/2010 - 6:30-7:45 p.m. - 26 Hosler Introduction to MIPS assembler, adds/loads/stores This week’s material MIPS control flow and logic operations - Reading assignment - PH 2.6 & 2.5 & 2.8-2.9 (1 st part) Next week’s material Supporting procedure calls and returns; addressing modes - Reading assignment - PH: 2.7 & 2.9, A.6, D.2
CSE331 W03.3 KB Spring 2008SP PSU

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CSE331 W03.4 KB Spring 2008SP PSU Review: Signed Binary Representation 2’sc binary decimal 1000 -8 1001 -7 1010 -6 1011 -5 -4 -3 -2 1111 -1 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 2 3 - 1 = -(2 3 - 1) = -2 3 = 1010 complement all the bits 1011 and add a 1 complement all the bits 0101 and add a 1 0110
CSE331 W03.5 KB Spring 2008SP PSU 32-bit signed numbers (2’s complement): 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten ... 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 Review: MIPS Number Representations maxint minint Converting <32 bit values into 32 bit values copy the most significant bit (the sign bit) into the “empty” bits 0010 -> 0000 0010 1010 -> 1111 1010 sign extend versus zero extend MSB LSB

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CSE331 W03.6 KB Spring 2008SP PSU Review: MIPS Organization Processor Memory 32 bits 2 30 words read/write addr read data write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 registers (\$zero - \$ra) 32 32 32 32 32 32 5 5 5 ALU 32 32 32 0 1 2 3 7 6 5 4 byte address (big Endian) Arithmetic instructions – to/from the register file Load/store instructions – from/to memory Fetch Decode Exec
CSE331 W03.7 KB Spring 2008SP PSU Review: MIPS Instructions, so far Category Instr OpCode Example Meaning Arithmetic (R format) add 0 & 20 add \$s1, \$s2, \$s3 \$s1 = \$s2 + \$s3 subtract 0 & 22 sub \$s1, \$s2, \$s3 \$s1 = \$s2 - \$s3 Arithmetic (I format) add immediate 8 addi \$s1, \$s2, 4 \$s1 = \$s2 + 4 Data transfer (I format) load word 23 lw \$s1, 100(\$s2) \$s1 = Memory(\$s2+100) store word 2b sw \$s1, 100(\$s2) Memory(\$s2+100) = \$s1 hex

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CSE331 W03.8 KB Spring 2008SP PSU Decision making instructions alter the control flow i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne \$s0, \$s1, Lbl #go to Lbl if \$s0 \$s1 beq \$s0, \$s1, Lbl #go to Lbl if \$s0=\$s1 Example: if (i==j) h = i + j; bne \$s0, \$s1, Lbl1 add \$s3, \$s0, \$s1 Lbl1: ... Instructions for Making Decisions
CSE331 W03.9 KB Spring 2008SP PSU Instructions: bne \$s0, \$s1, Lbl #go to Lbl if \$s0 \$s1 beq \$s0, \$s1, Lbl #go to Lbl if \$s0=\$s1 Machine Formats: How is the branch destination address specified? Assembling Branches op rs rt 16 bit number I format 5 16 17 ???? 4 16 17 ????

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CSE331 W03.10 KB Spring 2008SP PSU Specifying Branch Destinations Could use a “base” register and add to it the 16-bit offset which register?
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