218L10F08

# 218L10F08 - ESE218 Lecture 10 Arithmetic circuits Outline...

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10/14/08 ESE218 Fall 2008 Lecture 10 1 ESE218 Lecture 10: Arithmetic circuits Outline ± Binary Adders Half adder Full adder Ripple-carry adder Carry-lookahead adder ± Binary Subtractors ± 1’s complementer ± Subtraction by addition of a 2’s complement ± Overflow detection ± BCD Adder ± Summary

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10/14/08 ESE218 Fall 2008 Lecture 10 2 Half adder: a bit of history 1 1 0 0 X 1 0 0 0 C OUT 1 0 1 0 Y 0 1 1 0 Sum Sum C Y X OUT + George Stibitz (1904-1995) Vdc 0 13 11 9 4 6 8 16 1 Y 5 1 SUM 2 5 1 CARRYOUT 2 4 3 5 1 X 0 0 The first demonstration of use of relays for implementation of arithmetic operations
10/14/08 ESE218 Fall 2008 Lecture 10 3 Half adder: can add only two bits 1 2 3 1 2 3 1 2 3 4 5 6 1 2 3 4 1 2 3 2 3 1 1 1 0 0 X 1 0 0 0 C OUT 1 0 1 0 Y 0 1 1 0 Sum Sum C Y X OUT + Sum C out X Y X Y Sum C out Various implementations possible: XOR AND NOR OAI Sum with OAI: (X+Y’)(X’+Y) = X’Y+XY’ C out with NOR: (X’+Y’) = XY

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10/14/08 ESE218 Fall 2008 Lecture 10 4 Full adder: can add three bits 1 2 3 1 2 3 1 2 3 1 2 3 4 5 6 1 2 3 1 1 1 1 0 0 0 0 X 1 1 1 0 1 0 0 0 C OUT 1 1 0 0 1 1 0 0 Y 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 Sum C IN Sum C C Y X OUT IN + + Sum = X’Y’C in + X’YC in ’+ XY’C in ’+ XYC in (odd function) Carry-out = XY + XC in + YC in (too many gates needed) 001 010 100 111 <= m 1 +m 2 +m 4 +m 7 11- 1-1 -11 <= m 3 +m 5 +m 6 +m 7 6,7 5,7 3,7 Can one simplify the circuit for carry-out? X Y C in
10/14/08 ESE218 Fall 2008 Lecture 10 5 Full adder constructed with two half adders 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 7400 4 5 6 7400 9 10 8 7400 The idea is to utilize two half-adders for implementation of the 1-bit full adder

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218L10F08 - ESE218 Lecture 10 Arithmetic circuits Outline...

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