218L14F08 - ESE218 Lecture 14: Review of Latches,...

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10/28/08 ESE218 Fall 2008 Lecture 14 1 ESE218 Lecture 14: Review of Latches, Flip-flops Outline ± Review of SR-(NOR-based) and S’R’-(NAND-based) latches ± Gated (level-triggered) SR latch, D-latch ± Circuits with latches ± Edge-triggered SR-, D- flip-flops ± Setup and hold times ± Pulse-narrowing circuit ± Master-slave design ± Asynchronous CLEAR and PRESET ± Summary
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10/28/08 ESE218 Fall 2008 Lecture 14 2 SR-latch: summary and timing diagram 5 6 4 8 9 10 Q Q’ R S Q Q’ R S • NOR-based circuit important: top input is RESET (if output Q is on top) •Act ive- HIGH inputs (SR=10 for SET; SR=01 for RESET; SR=00 for HOLD) 0 -dominant outputs
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10/28/08 ESE218 Fall 2008 Lecture 14 3 S’R’-latch: summary and timing diagram 1 2 3 4 5 6 RESET SET Q Q’ Q Q’ R S • NAND-based circuit important: top input is SET (if output Q is on top) •Act ive- LOW inputs (SR=01 for SET, SR=10 for RESET, SR=11 for hold) 1 -dominant outputs (both outputs = 1 when both inputs are active: SR=00) SR and S’R’ latches have a serious drawback: the outputs can not be always
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10/28/08 ESE218 Fall 2008 Lecture 14 4 Gated SR-latch 1 2 3 4 5 6 9 10 8 4 5 6 S G R Q Q’ Q S R G G Q S R Gating the inputs with G helps overcoming a chance of having
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This note was uploaded on 03/21/2010 for the course ESE 218 taught by Professor Donetsky during the Fall '08 term at SUNY Stony Brook.

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218L14F08 - ESE218 Lecture 14: Review of Latches,...

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