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218L15F08 - ESE218 Lecture 15 Latches and Flip-flops...

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10/30/08 ESE218 Fall 2008 Lecture 15 1 ESE218 Lecture 15: Latches and Flip-flops Outline Asynchronous CLEAR and PRESET JK-latch and JK-flip-flop T-flip-flop Flip-flop conversions Analysis of sequential circuits Mealy- and Moore- output types Summary
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10/30/08 ESE218 Fall 2008 Lecture 15 2 Asynchronous inputs: PRESET and CLEAR 1 2 3 4 5 6 9 10 8 4 5 6 S CLK Q Q’ CLR Q S R Asynchronous inputs CLEAR, PRESET have the highest priority: if active - they take control on output and override action of synchronous inputs SET, RESET PRESET CLEAR CLK PRT Q S PRT R CLR CLK R Static inputs (asynchronous) Dynamic inputs (synchronous with clock)
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10/30/08 ESE218 Fall 2008 Lecture 15 3 JK-latch K Q Q’ Q J K CLK CLK Q J K 1 2 3 4 5 6 J CLK S R Q*= JQ’ + K’Q Q*= S + R’Q = JQ’+(KQ)’Q
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10/30/08 ESE218 Fall 2008 Lecture 15 4 1 2 1 2 3 4 5 6 1 2 3 JK-flip-flop K Q Q J K CLK J CLK D Q’ Q J K CLK
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10/30/08 ESE218 Fall 2008 Lecture 15 5 T-flip-flop T Q T CLK CLK Q T Q J K CLK
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10/30/08 ESE218 Fall 2008 Lecture 15 6 Synchronous FSM Present state Input clock FF 0 FF n Next state
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  • Fall '08
  • DONETSKY
  • CLK K CLK