218L17F08 - 2. D latch Flip-flops 1. Edge-triggered...

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4/3/08 ESE218 Fall 2008 Review 2 1 Topics for Test 2 Combinational circuit design 1. Code converters 2. ARITHMETIC CIRCUITS Half and full adders Ripple adder Carry-lookahead adder carry generate and carry propagate 2’s complementer Adder/subtractor Overflow detection BCD adder 3. Magnitude comparators
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4/3/08 ESE218 Fall 2008 Review 2 2 Topics for Test 2 1. Decoders active low outputs active-high outputs enable inputs and expansion to larger number of inputs IMPLEMENTATION OF SWITCHING FUNCTIONS 2. Priority encoders 3. Multiplexers expansion to larger number of inputs IMPLEMENTATION OF SWITCHING FUNCTIONS
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4/3/08 ESE218 Fall 2008 Review 2 3 Topics for Test 2 Latches 1. SR latch (NOR-based) and S’R’ latch (NAND-based), SR latch with Gate (CLK) input (NAND-based circuit) active-low and active high inputs state table TIMING DIAGRAMS
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Unformatted text preview: 2. D latch Flip-flops 1. Edge-triggered D-flip-flops: masterslave design negative edge- and positive edge triggering 2. JK- and T- flip-flops state tables characteristic equations TIMING DIAGRAMS 3. Asynchronous (static) inputs preset and clear TIMING DIAGRAMS 4/3/08 ESE218 Fall 2008 Review 2 4 Topics for Test 2 Test 2 WILL include up to 25 questions grouped in several problems in accordance with covered topics Review the textbook (Chapters 4 and 5) 2. Review assignments for lab. experiments 3. Review HW solutions 4. Practice solving problems - the test time is limited Analysis of synchronous circuits with edge-triggered flip-flops (expect circuits with 1-2 flip-flops) 1. D-FF 2. T FF 3. JK-FF Design of synchronous circuits with FF (additional questions)...
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218L17F08 - 2. D latch Flip-flops 1. Edge-triggered...

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