218L18F08 - ESE218 Lecture 18: Synchronous counters Outline...

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11/13/08 ESE218 Fall 2008 Lecture 18 1 ESE218 Lecture 18: Synchronous counters Outline ± General structure ± single-mode counters ± multi-mode counters ± Design with D-flip-flops ± State diagram ± State table ± Excitation equation ± Timing diagrams for illustration ± Design with T-flip-flops ± Design with JK-flip-flops ± Input Excitation ± Timing diagrams ± Max operating frequency ± Summary
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11/13/08 ESE218 Fall 2008 Lecture 18 2 Single–mode synchronous counters Q 1 Q 0 FF 0 FF 1 CLK Combinational circuit Q 2 FF 2 O u t p u t s NO INPUTS
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11/13/08 ESE218 Fall 2008 Lecture 18 3 Multi–mode synchronous counters Q 1 Q 0 FF 0 FF 1 CLK Combinational circuit Q 2 FF 2 O u t p u t s Control input(s) X Example: counting UP with X =0 counting DOWN with X=1
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11/13/08 ESE218 Fall 2008 Lecture 18 4 Single mode counters: binary counter with D-flip-flops 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 Req. inputs D 2 D 1 D 0 (the same as N.S. for D-flip-flops) Next State Q* 2 Q* 1 Q* 0 Present State Q 2 Q 1 Q 0 D 0 = Q’ 0 D 1 = Q 1 Q’ 0 +Q’ 1 Q 0 D 2 = Q 2 Q’ 1 + Q’ 2 Q 1 Q 0 + Q 2 Q’ 0 (Characteristic equations: Q i *=D i ; i=0,1,2 ) State table -> FF excitation = Solution 1 1 Q 2 = 1 1 1 Q 2 = 0 10 11 01 00 Q 1 Q 0 = 1 1 Q 2 = 1 1 1 Q 2 = 0 10 11 01 00 Q 1 Q 0 = 1 1 1 Q 2 = 1 1 Q 2 = 0 10 11 01 00 Q 1 Q 0 =
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11/13/08 ESE218 Fall 2008 Lecture 18 5 Circuit schematic and timing diagrams Q 2 CLK Q 1 Q 0 Moore-output model: No glitches can occur at the outputs
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This note was uploaded on 03/21/2010 for the course ESE 218 taught by Professor Donetsky during the Fall '08 term at SUNY Stony Brook.

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218L18F08 - ESE218 Lecture 18: Synchronous counters Outline...

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