218L19F08 - 11/18/08 ESE218 Fall 2008 Lecture 19 1 ESE218...

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Unformatted text preview: 11/18/08 ESE218 Fall 2008 Lecture 19 1 ESE218 Lecture 19: Registers Outline Asynchronous counters with CLEAR Registers P structure registers with parallel load shift registers timing diagram Register-based synchronous counters ring counter Johnson counter state decoding hang-up states self-correction Summary 11/18/08 ESE218 Fall 2008 Lecture 19 2 Asynchronous binary counters: no need in input excitation circuit Q T CLK 1 Q 1 T 1 Q 2 T 1 000 111 111 110 110 101 101 100 100 011 011 010 010 001 001 000 Next state Present state Counting UP is obtained with NEGATIVE-EDGE-triggered flip-flops Absence of FF synchronization leads to accumulation of prop. delay with T =1 for each flip-flop Q*= Q 11/18/08 ESE218 Fall 2008 Lecture 19 3 Asynchronous binary counters: T-FF can be with replaced with D-FF without input excitation circuit (Q* =Q) 111 110 101 100 011 010 001 000 Next state Present state Q D CLK Q 1 D Q 2 D CLR POSITIVE-EDGE triggering results in counting DOWN Optional CLEAR inputs can be handy in control on initial state 11/18/08...
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218L19F08 - 11/18/08 ESE218 Fall 2008 Lecture 19 1 ESE218...

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