218L23F08 - ESE218 Lecture 23: State reduction. Outline...

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12/9/08 ESE218 Fall 2008 Lecture 23 1 ESE218 Lecture 23: State reduction. Outline ± General design procedure ± State equivalence ± State reduction ± row matching ± implication chart ± partitioning ± Summary
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12/9/08 ESE218 Fall 2008 Lecture 23 2 General design procedure 1. Construction of the initial state diagram that realizes the algorithm 2. State minimization 3. State encoding 4. Selection of registers for state memory 5. Implementation of the next states (equations for flip-flop inputs) 6. Implementation of output functions 7. Design verification
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12/9/08 ESE218 Fall 2008 Lecture 23 3 State equivalence Two states are equivalent and can be combined into a single state if the following conditions met: A. Both states produce the same output Z for every input X B. The next states produce the same outputs Z for every input X Output values of two states are the same for every finite input sequence
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12/9/08 ESE218 Fall 2008 Lecture 23 4 3-bit sequence detector without overlapping: state diagram
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218L23F08 - ESE218 Lecture 23: State reduction. Outline...

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