218L24F08 - 12/11/08 ESE218 Fall 2008 Lecture 24 1 ESE218...

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Unformatted text preview: 12/11/08 ESE218 Fall 2008 Lecture 24 1 ESE218 Lecture 24. Programmable Logic. Memory elements Outline Programmable logic ROM PAL PLA Sequential devices CPLD FPGA Memory RAM Static Dynamic Summary 12/11/08 ESE218 Fall 2008 Lecture 24 2 Memory array structure Read Write . . . Address decoder Address bus Data bus Memory array 12/11/08 ESE218 Fall 2008 Lecture 24 3 Read-Only Memory 1 2 3 4 5 6 1 12 2 1 3 6 4 5 9 8 10 11 3 6 4 5 9 8 10 11 3 6 4 5 3 6 4 5 9 8 10 11 1 2 3 4 5 6 12/11/08 ESE218 Fall 2008 Lecture 24 4 Read Only Memory Address decoder Address bus Data output Vdd=+5v Vdd=+5v 12/11/08 ESE218 Fall 2008 Lecture 24 5 Programmable Array Logic 1 2 3 4 5 6 1 12 2 13 3 6 4 5 9 8 10 11 3 6 4 5 9 8 10 11 3 6 4 5 3 6 4 5 9 8 10 11 1 2 3 4 5 6 12/11/08 ESE218 Fall 2008 Lecture 24 6 Programmable Logic Array 1 2 3 4 5 6 1 12 2 13 3 6 4 5 9 8 10 11 3 6 4 5 9 8 10 11 3 6 4 5 3 6 4 5 9 8 10 11 1 2 3 4 5 6 12/11/08 ESE218 Fall 2008 Lecture 24 7 Programmable Logic Devices 1 2 3 4 5 6 1 12 2 13 3 6 4 5 9 8 10 11 3 6 4 5 9 8 10 11 3 6 4 5 3 6 4 5 9 8 10 11 1 2 3 4 5 6 D 2 CLK 3 Q 5 Q 6 PR 4 CL 1 12/11/08...
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218L24F08 - 12/11/08 ESE218 Fall 2008 Lecture 24 1 ESE218...

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