ch12[1] - Computer System Architecture Dept. of Info. Of...

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Unformatted text preview: Computer System Architecture Dept. of Info. Of Computer. Chap. 12 Memory Organization Chap. 12 Memory Organization 12-1 Chap. 12 Memory Organization 12-1 Memory Hierarchy Memory hierarchy in a computer system : Fig. 12-1 Main Memory : memory unit that communicates directly with the CPU ( RAM ) Auxiliary Memory : device that provide backup storage ( Disk Drives ) Cache Memory : special very-high-speed memory to increase the processing speed ( Cache RAM ) Multiprogramming enable the CPU to process a number of independent program concurrently Memory Management System : sec. 12-7 Magnetic tapes Magnetic disks I/ O processor CPU Main memory Cache memory Auxiliary memory Computer System Architecture Dept. of Info. Of Computer. Chap. 12 Memory Organization Chap. 12 Memory Organization 12-2 12-2 Main Memory Bootstrap Loader A program whose function is to start the computer software operating when power is turned on RAM and ROM Chips Typical RAM chip : Fig. 12-2 128 X 8 RAM : 2 7 = 128 ( 7 bit address lines ) Typical ROM chip : Fig. 12-3 512 X 8 ROM : 2 9 = 512 ( 9 bit address lines ) 128 8 RAM CS1 AD7 WR RD CS2 Chip select 1 Chip select 2 Read Write 7 bit address 8 bit data bus (a) Block diagram CS1 WR RD CS2 Memory function State of data bus 1 1 1 1 1 1 1 1 Inhibit Inhibit Inhibit Write Read Inhibit High- impedance High- impedance High- impedance Input data to RAM Output data from RAM High- impedance (b) Function table 512 8 ROM CS1 AD9 CS2 Chip select 1 Chip select 2 9 bit address 8 bit data bus Po w e r- O N FFFF:0 0 0 0 (Re s e t P o in t) P O ST Sys te m In it. IN T 1 9 Lo a d B o o ts tra p Re c o rd (Tra c k 0 , Se c to r 0 ) Lo a d O p e ra tin g Sys te m (IO . SYS, M SD O S. SYS, C O M M AN D . C O M ) Bootstrap Loader Bootstrap ROM Boot ROM Computer System Architecture Dept. of Info. Of Computer. Chap. 12 Memory Organization Chap. 12 Memory Organization 12-3 Memory Address Map Memory Configuration : 512 bytes RAM + 512 bytes ROM 1 x 512 byte ROM + 4 x 128 bytes RAM Memory Address Map : Tab. 12-1 Address line 9 8 RAM 1 0 0 : 0000 - 007F RAM 1 0 1 : 0080 - 00FF RAM 1 1 0 : 0100 - 017F RAM 1 1 1 : 0180 - 01FF Address line 10 ROM 1 : 0200 - 03FF Memory Connection to CPU : Fig. 12-4 2 x 4 Decoder : RAM select ( CS1 ) Address line 10 RAM select : CS2 ROM select : CS2 o Invert h& RD : ROM o CS1 p && OE(Output Enable) 128 8 RAM 1 CS1 AD7 WR RD CS2 128 8 RAM 2 CS1 AD7 WR RD CS2 128 8 RAM 4 CS1 AD7 WR RD CS2 128 8 RAM 3 CS1 AD7 WR RD CS2 128 8 ROM CS1 CS2 AD9 Data Data Data Data Data CPU WR RD 16 - 11 10 9 8 7 - 1 Address bus Data bus Decoder 3 2 1 1- 7 8 9 Computer System Architecture Dept. of Info. Of Computer....
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This note was uploaded on 03/21/2010 for the course CS 145 taught by Professor Markjan during the Spring '10 term at Abilene Christian University.

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ch12[1] - Computer System Architecture Dept. of Info. Of...

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