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ch12[1] - Chap. s 121 12-1 Memory Hierarchy Memory...

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Computer System Architecture Dept. of Info. Of Computer. Chap. 12 Memory Organization Chap. 12 12-1 Chap. 12  Memory Organization 12-1 Memory Hierarchy Memory hierarchy in a computer system : Fig. 12-1 Main Memory : memory unit that communicates directly with the CPU ( RAM ) Auxiliary Memory : device that provide backup storage ( Disk Drives ) Cache Memory : special very-high-speed memory to increase the processing speed ( Cache RAM ) Multiprogramming enable the CPU to process a number of independent program concurrently Memory Management System : sec. 12-7 supervise the flow of information between auxiliary memory and main memory M a g n e t i c t a p e s M a g n e t i c d i s k s I / O p r o c e s s o r C P U M a i n m e m o r y C a c h e m e m o r y A u x i l i a r y m e m o r y
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Computer System Architecture Dept. of Info. Of Computer. Chap. 12 Memory Organization Chap. 12 12-2 12-2 Main Memory Bootstrap Loader A program whose function is to start the computer software operating when power is turned on RAM and ROM Chips Typical RAM chip : Fig. 12-2 » 128 X 8 RAM : 2 7 = 128 ( 7 bit address lines ) Typical ROM chip : Fig. 12-3 » 512 X 8 ROM : 2 9 = 512 ( 9 bit address lines ) × 1 2 8 × 8 R A M C S 1 A D 7 W R R D C S 2 C h i p s e l e c t 1 C h i p s e l e c t 2 R e a d W r i t e 7 b i t a d d r e s s 8 b i t d a t a b u s ( a ) B l o c k d i a g r a m C S 1 W R R D C S 2 M e m o r y f u n c t i o n S t a t e o f d a t a b u s 0 × × × 0 0 0 0 0 0 1 1 1 1 1 1 × 0 × × 0 1 1 I n h i b i t I n h i b i t I n h i b i t W r i t e R e a d I n h i b i t H i g h - i m p e d a n c e H i g h - i m p e d a n c e H i g h - i m p e d a n c e I n p u t d a t a t o R A M O u t p u t d a t a f r o m R A M H i g h - i m p e d a n c e ( b ) F u n c t i o n t a b l e 5 1 2 × 8 R O M C S 1 A D 9 C S 2 C h i p s e l e c t 1 C h i p s e l e c t 2 9 b i t a d d r e s s 8 b i t d a t a b u s P o w e r - O N F F F F : 0 0 0 0 ( R e s e t P o i n t ) P O S T S y s t e m I n i t . I N T 1 9 L o a d B o o t s t r a p R e c o r d ( T r a c k 0 , S e c t o r 0 ) L o a d O p e r a t i n g S y s t e m ( I O . S Y S , M S D O S . S Y S , C O M M A N D . C O M ) Bootstrap Loader Bootstrap ROM Boot ROM
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Computer System Architecture Dept. of Info. Of Computer. Chap. 12 Memory Organization Chap. 12 12-3 Memory Address Map Memory Configuration : 512 bytes RAM + 512 bytes ROM » 1 x 512 byte ROM + 4 x 128 bytes RAM Memory Address Map : Tab. 12-1 » Address line 9 8 RAM 1 0 0 : 0000 - 007F RAM 1 0 1 : 0080 - 00FF RAM 1 1 0 : 0100 - 017F RAM 1 1 1 : 0180 - 01FF » Address line 10 ROM 1 : 0200 - 03FF Memory Connection to CPU : Fig. 12-4 » 2 x 4 Decoder : RAM select ( CS1 ) » Address line 10 RAM select : CS2 ROM select : CS2 o Invert » RD : ROM o CS1 p °° OE(Output Enable) & 1 2 8 × 8 R A M 1 C S 1 A D 7 W R R D C S 2 1 2 8 × 8 R A M 2 C S 1 A D 7 W R R D C S 2 1 2 8 × 8 R A M 4 C S 1 A D 7 W R R D C S 2 1 2 8 × 8 R A M 3 C S 1 A D 7 W R R D C S 2 1 2 8 × 8 R O M C S 1 C S 2 A D 9 D a t a D a t a D a t a D a t a D a t a C P U W R R D 1 6 - 1 1 1 0 9 8 7 - 1 A d d r e s s b u s D
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