ch09 - Computer System Architecture Dept. of Info. Of...

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Unformatted text preview: Computer System Architecture Dept. of Info. Of Computer Chap. 9 Pipeline and Vector Processing Chap. 9 Pipeline and Vector Processing 9-1 Chap. 9 Pipeline and Vector Processing ■ 9-1 Parallel Processing Simultaneous data processing tasks for the purpose of increasing the computational speed Perform concurrent data processing to achieve faster execution time Multiple Functional Unit : Fig. 9-1 ● Separate the execution unit into eight functional units operating in parallel Computer Architectural Classification ● Data-Instruction Stream : Flynn ● Serial versus Parallel Processing : Feng ● Parallelism and Pipelining : Händler Flynn’s Classification ● 1) SISD ( Single Instruction - Single Data stream ) » for practical purpose: only one processor is useful » Example systems : Amdahl 470V/6, IBM 360/91 Parallel Processing Example Adder- subtractor Integer multiply Floatint- point add- subtract Incrementer Shift unit Logic unit Floatint- point divide Floatint- point multiply Processor registers To Memory = CU MM PU IS DS IS Computer System Architecture Dept. of Info. Of Computer Chap. 9 Pipeline and Vector Processing Chap. 9 Pipeline and Vector Processing 9-2 ● 2) SIMD ( Single Instruction - Multiple Data stream ) » vector or array operations & S ¶ “ ¡¡ ■ one vector operation includes many operations on a data stream » Example systems : CRAY -1, ILLIAC-IV ● 3) MISD ( Multiple Instruction - Single Data stream ) » Data Stream o Bottle neck &N ¶ “ ¡¡ ( · CU PU 1 PU n PU 2 MM 1 MM n MM 2 DS 1 DS 2 DS n IS IS Shared memmory PU 1 PU n PU 2 DS CU 1 CU n CU 2 IS 1 IS 2 IS n MM 1 MM n MM 2 IS 1 IS 2 IS n DS Shared memory Computer System Architecture Dept. of Info. Of Computer Chap. 9 Pipeline and Vector Processing Chap. 9 Pipeline and Vector Processing 9-3 ● 4) MIMD ( Multiple Instruction - Multiple Data stream ) » H , O · Multiprocessor System H , · “E Main topics in this Chapter ● Pipeline processing : Sec. 9-2 » Arithmetic pipeline : Sec. 9-3 » Instruction pipeline : Sec. 9-4 ● Vector processing : adder/multiplier pipeline o& , Sec. 9-6 Large vector, Matrices, e Array Data e PU 1 PU n PU 2 DS CU 1 CU n CU 2 IS 1 IS 2 IS n IS 1 IS 2 IS n MM 1 MM n MM 2 Shared memory v v Computer System Architecture Dept. of Info. Of Computer Chap. 9 Pipeline and Vector Processing Chap. 9 Pipeline and Vector Processing 9-4 ■ 9-2 Pipelining Pipelining p && ● Decomposing a sequential process into suboperations ● Each subprocess is executed in a special dedicated segment concurrently Pipelining ¡ P ¶ : Fig. 9-2 ● Multiply and add operation : ( for i = 1, 2, …, 7 ) ● 3 o& Suboperation Segment p && » 1) : Input Ai and Bi » 2) : Multiply and input Ci » 3) : Add Ci ● Content of registers in pipeline example : Tab. 9-1 General considerations ● 4 segment pipeline : Fig. 9-3 » S : Combinational circuit for Suboperation » R : Register( intermediate results between the segments...
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This note was uploaded on 03/21/2010 for the course CS 145 taught by Professor Markjan during the Spring '10 term at Abilene Christian University.

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ch09 - Computer System Architecture Dept. of Info. Of...

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