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ch08 - Chap. s 81 8-1 Introduction 3 major parts of CPU Fig...

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Computer System Architecture Dept. of Info. Of Computer Chap. 8 Central Processing Unit Chap. 8 Central Processing Unit 8-1 Chap. 8  Central Processing Unit 8-1 Introduction 3 major parts of CPU : Fig. 8-1 1) Register Set 2) ALU 3) Control Design Examples of simple CPU Hardwired Control : Chap. 5 Microprogrammed Control : Chap. 7 In this chapter : Chap. 8 Describe the organization and architecture of the CPU with an emphasis on the user’s view of the computer User who programs the computer in machine/assembly language must be aware of » 1) Instruction Formats » 2) Addressing Modes » 3) Register Sets The last section presents the concept of Reduced Instruction Set Computer ( RISC ) Computer Architecture as seen by the programmer Chap. 8 h :
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Computer System Architecture Dept. of Info. Of Computer Chap. 8 Central Processing Unit Chap. 8 Central Processing Unit 8-2 8-2 General Register Organization i ± Memory locations are needed for storing pointers, counters, return address, temporary results, and partial products during multiplication ( in the programming examples of Chap. 6 ) Memory access is the most time-consuming operation in a computer More convenient and efficient way is to store intermediate values in processor registers Bus organization for 7 CPU registers : Fig. 8-2 2 MUX : select one of 7 register or external data input by SELA and SELB BUS A and BUS B : form the inputs to a common ALU ALU : OPR determine the arithmetic or logic microoperation » The result of the microoperation is available for external data output and also goes into the inputs of all the registers 3 X 8 Decoder : select the register (by SELD ) that receives the information from ALU R 1 R 2 R 4 R 3 R 6 R 7 R 5 3 × 8 d e c o d e r M U X M U X A r i t h m e t i c l o g i c u n i t ( A L U ) C l o c k I n p u t L o a d ( 7 l i n e s ) S E L A S E L B A b u s B b u s O P R O u t p u t S E L D ( a ) B l o c k d i a g r a m ( b ) C o n t r o l w o r d S E L A S E L D S E L B O P R 3 5 3 3 External Output External Input
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Computer System Architecture Dept. of Info. Of Computer Chap. 8 Central Processing Unit Chap. 8 Central Processing Unit 8-3 1) MUX A selector ( SELA ) : to place the content of R2 into BUS A 2) MUX B selector ( SELB ) : to place the content of R3 into BUS B 3) ALU operation selector ( OPR ) : to provide the arithmetic addition R2 + R3 4) Decoder selector ( SELD ) : to transfer the content of the output bus into R1 Control Word 14 bit control word ( 4 fields ) : Fig. 8-2(b) » SELA ( 3 bits ) : select a source register for the A input of the ALU » SELB ( 3 bits ) : select a source register for the B input of the ALU » SELD ( 3 bits ) : select a destination register using the 3 X 8 decoder » OPR ( 5 bits ) : select one of the operations in the ALU Encoding of Register Selection Fields : Tab. 8-1 » SELA or SELB = 000 ( Input ) : MUX selects the external input data » SELD = 000 ( None ) : no destination register is selected but the contents of the output
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ch08 - Chap. s 81 8-1 Introduction 3 major parts of CPU Fig...

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