tarea - * 09/07/09 13:29:51 * PSpice 16.2.0 (Oct 2008) *...

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* * Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ; **** CIRCUIT DESCRIPTION ****************************************************************************** * * TDB File: C:\Users\juanchirilin\Uniandes\Segundo semestre\DIGITALES\L- edit\archivos TDB\cascadainversor, Cell: Cell0 * Extract Definition File: C:\Users\juanchirilin\Uniandes\Segundo semestre\DIGITALES\L-edit\tecnologias\CNM25\CNM25.EXT * Extract Date and Time: 09/07/2009 - 13:27 * * WARNING: Layers with Unassigned FRINGE Capacitance. * <EXT-Capacidad poly> * WARNING: Layers with Zero Resistance. * <EXT-Capacidad poly> * * NODE NAME ALIASES * 1 = Vdd (-45,28) * 2 = Gnd (-44.25,-17.75) * 3 = Out1 (-1.25,-4.75) * 4 = Out2 (-35.25,-4.25) * 5 = Out3 (-58.5,3.5) * 6 = Out (33.5,-5) * 7 = In (62.25,3.5) * * THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS .model PMOS PMOS LEVEL = 2 + TOX = 380E-10 VTO = -1.139 NSUB = 1.355E16 UO = 212.7 + UCRIT = 1E4 UEXP = .1159 NFS = 662.4E9 WD = .4268E-6 + DELTA = 1.824 RS = 134.9 LD = .8101E-6 XJ = 2.783E-9 + VMAX = 120.3E3 NEFF = .06665 CJ = 3.816E-4 MJ = .3499 + CJSW = 7.384E-10 MJSW = .3916 PB = .56 + .model NMOS NMOS LEVEL = 2 + TOX = 380E-10 VTO = .9418 NSUB = 2.639E16 UO = 648.2 + UCRIT = 1E4 UEXP = .06857 NFS = 710.8E9 WD = .4086E-6 + DELTA = 2.2 RS = 93.77 LD = .9132E-6 XJ = .0824E-6 + VMAX = 59.62E3 NEFF = 1.479 CJ = 3.495E-4 MJ = .3950 + CJSW = 5.952E-10 MJSW = .2941 PB = .65 + VDD Vdd 0 DC 5V VIN In 0 PULSE(0 4.6 1n 0.1n 0.1n 3n 5n) Vsc Gnd 0 DC 0V V M1 Vdd Out1 Out2 Vdd PMOS L=2.5u W=2.5u * M1 DRAIN GATE SOURCE BULK (-17 10 -14.5 12.5) M2 Vdd Out2 Out3 Vdd PMOS L=2.5u W=2.5u * M2 DRAIN GATE SOURCE BULK (-50.5 10 -48 12.5) M3 Vdd Out Out1 Vdd PMOS L=2.5u W=2.5u
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This note was uploaded on 03/23/2010 for the course ELECTRONIC mems taught by Professor Juanariza during the Spring '10 term at 東京国際大学.

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tarea - * 09/07/09 13:29:51 * PSpice 16.2.0 (Oct 2008) *...

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