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Unformatted text preview: Chapter 8 Sequential networks
In this chapter we discuss: Canonical form of sequential networks: state register plus combinational network. Characteristics of binary cells: latches and edgetriggered cells. The D ip op. Timing parameters for cells and networks: setup time, hold time, and propagation delay. Example for a family of cmos modules. Analysis and design of canonical networks. Other ip op modules: SR, JK and T ip op. Tables, state diagrams and characteristic equations. Analysis of ip op networks. Design of ip op networks. The excitation functions. Special state assignments: one ip opperstate and shifting register. Speci cation of sequential networks in vhdl. In the same way as for combinational systems (see Chapter 4), the realization of a sequential system involves a circuit level and a logic level. The circuit level deals with the physical realization of elementary sequential modules. In contrast, the logic level consists of the realization of a sequential system by a collection of simpler networks, both combinational and sequential, leading to a sequential network. As in the case of combinational systems, the network concept can be used at several levels in a hierarchical manner (a module in a network can itself be realized as a network of simpler modules). We begin studying the realization of synchronous sequential systems by showing a canonical implementation, which consists of a set of binary cells 257 258 Chapter 8. Sequential networks to store the state and combinational networks to realize the output and transition functions. Consequently, the only additional element required for the implementation is the binary cell. We show how this cell, called the D ipop, can be realized by a gate network in which the sequential operation is achieved by a loop in the network. A standard form for all sequential networks is the canonical implementation (also called Hu manMoore implementation), which is based directly on the state description of a system: Statetransition function s(t + 1) = G(s(t); x(t)) Output function z (t) = H (s(t); x(t)) This implementation, whose components are organized as depicted in Figure 8.1a, consists of a state register to store the state; and a combinational network to implement the transition and output functions. Since the system is synchronous, a synchronizing signal (called the clock CLK) determines the time instants at which the next state is loaded into the state register. At time t, the next state is loaded into the state register and remains stored there until time t + 1. The clock consists of periodic clock pulses (see Figure 8.1b), which in the ideal case have zero width. Actual clock pulses, whose nonzero width a ects the operation of the sequential network, are discussed in Section 8.3. In general, the description of a sequential system includes an initial state, being necessary to bring the system into such a state in order to have the desired inputoutput behavior. This initialization is accomplished by a special input initialize. For simplicity, in this book we usually do not indicate the initialization signal but assume that it is implemented as required. From the discussion in Section 7.1.3, any sequential system is classi ed either as a Mealy or Moore machine. The canonical form of these systems di er slightly, as illustrated in Figure 8.2. In a Mealy machine, the networks for both the transition function and the output function have the external input x(t) and the state s(t) as inputs, whereas in a Moore machine the network implementingthe output function has only s(t) as input. It should be noted that the separation of the combinational network into two independent subnetworks is made only to illustrate the di erence; in a practical implementation, this separation would not necessarily be made because both networks could share some modules. 8.1 Canonical form of sequential networks 8.1. Canonical form of sequential networks 259 State Register Combinational Network next state
s(t+1) initialize present input
x(t) s(t) present state CLK z(t) (a) present output Ideal clock pulse PRESENT STATE s(t) t NEXT STATE s(t+1) Ideal clock t
0 1 2 3 4 5 (b) 6 7 Figure 8.1: a) Canonical implementation of sequential network. b) Ideal clock signal and its interpretation. 260 Chapter 8. Sequential networks s(t+1) C1 x(t) State Register s(t) C2 z(t) CLK (a) State Register s(t+1) C1 x(t) z(t) C2 s(t) CLK (b) Figure 8.2: Canonical implementations: a) Mealy machine. b) Moore machine. 8.2. Highlevel and binary implementations
Initialize z0 Y0 Y1 Y k1 y y y Outputs z n1
0 1 261 Inputs x m1 x0 Combinational Network State Register (binary cells)
k1 Next state Present state CLK Figure 8.3: Canonical implementation with binary variables. 8.2 Highlevel and binary implementations
The highlevel description of the canonical form of a sequential system uses multivalued variables for input, state and output. This compact and manageable description is used whenever the particular binary representation is not signi cant. On the other hand, as we have discussed for combinational networks, the physical implementation of digital systems uses binary variables. Consequently, a highlevel description must be converted into a binary description by introducing codes for the input, output, and state variables, so that the variables x, s, and z are represented by the bitvectors x, s, and z , respectively. The canonical form of a binary system is illustrated in Figure 8.3. In this implementation, the state register consists of k binary cells, wherein k is the number of state variables. Each binary cell has a binary input (the next state), a binary output (the present state), and a synchronizing input (the clock). As depicted in the gure, it is customary to denote the presentstate vector (PS ) by y and the nextstate vector (NS ) by Y . Example 8.1 Figure 8.4 depicts the (binary) canonical form of a sequential
system having the following description: 262
x0 x1 Initialize Combinational Network Y0 Y1 Y2 Y3 y
0 Chapter 8. Sequential networks y 1 y 2 y
3 z CLK Figure 8.4: Canonical network for Example 8.1. Input: Output: State: Initial state: Function: x(t) = (x1 ; x0); xi 2 f0; 1g z (t) 2 f0; 1g y (t) = (y3 ; y2 ; y1; y0 ); yi (t) 2 f0; 1g y (0) = (0; 0; 0; 0) The transition and output functions are Y3 Y2 Y1 Y0 = = = = y2 x01x0 (y1 y2 )x00 y3 x1 (y0 y3 )x01 x0 (y0 y1 )x1 (y0 y3 )x00 y1 x01x0 y2 x1 z = y3 y2 y1 y0 8.3 Gatedlatch and D ip op
So far we have considered the ideal case in which the clock pulse has zero width, and the binary cells change state instantaneously. In practice, the clock pulse has a nite width and the cell has some timing characteristics that have to be taken into account for a satisfactory operation of a system. These characteristics also determine the speed of the resulting network. The basic characteristics of the clock signal with respect to network timing, depicted in Figure 8.5, are the clock period T (or the clock frequency f = 1=T ); and 8.3. Gatedlatch and D ip op
CLK t
w 263 Clock pulse width Clock period T time Figure 8.5: Pulse width and clock period. the (clock) pulse width tw . Let us now consider the characteristics required from binary cells so that they perform adequately in a synchronous sequential network. The most basic binary cell is called a (controlled) gatedlatch; it has one binary input signal D (for data), one binary output signal Q, and an enable input E , as shown in Figure 8.6a. The output of the cell corresponds to the state; this output follows the value of the input when E = 1 and does not change (is latched) when E = 0, so the cell is called levelsensitive (in contrast to the edgesensitive cell discussed later) The change of value of the output signal has a propagation delay tp with respect to a change in the enable signal (see Figure 8.6b). That is, Q(t + tp ) = D(t) E (t) Q(t) E 0 (t) Figures 8.7 and 8.8 show two alternative implementations of a gatedlatch. These implementations consist of a gate network which includes a loop that is responsible for storing the state. In the rst implementation, the loop consists of two nor gates. The operation, illustrated by the timing diagram in Figure 8.7b (wherein the arrows indicate \causee ect" relations among signal changes), is as follows: When E = 1, signals b and d correspond to the value of D and D0 , respectively. Two situations can occur: if b = 1 and d = 0, then c = 0 and Q = 1; and if b = 0 and d = 1, then Q = 0 and c = 1. Consequently, in both cases Q = D. When E = 0, b = d = 0 and the loop is used to latch the value of Q. In the second implementation (see Figure 8.8), the operation is as follows: When E = 1, the upper transmission gate corresponds to a closed switch and the lower transmission gate corresponds to an open switch. Therefore, the value of the output Q is equal to the input D. 264 Chapter 8. Sequential networks D Q E (a) E D Q t p t p (b) Figure 8.6: a) Gatedlatch. b) Timing behavior. 8.3. Gatedlatch and D ip op 265 D (Input) b c E (Enable) a d Q (Output) (a) E D a b c d Q * c kept in 0 even when b=0 + Q kept in 0 even when d=0 (b) loop * + loop Figure 8.7: a) Implementation of gatedlatch with nor gates. b) Timing diagram. 266
TG1 D (Input) E (Enable) c b d a TG2 Chapter 8. Sequential networks Q (Output) e f (a) E a b TG1 TG2 D c d f Q loop loop on on off off (b) diagram. Figure 8.8: a) Implementation of gatedlatch with transmission gates. b) Timing When E = 0, the situation reverses so that the input is disconnected from the output and the twoinverter loop maintains the state. In both implementations, the (noninverting) loop is the basis for the operation of the network as a sequential system.1 In the second implementation, the inverters in the loop are needed to compensate for the voltage drop across the transmission gate. Limitations of gatedlatch for use in a synchronous network
The gatedlatch could be used in a synchronous sequential system by connecting the clock to input E , but this might not produce the desired behavior. To show
1 An inverting loop produces an oscillator, in which the output changes periodically from 0 to 1 to 0, the period depending on the delay in the loop. 8.3. Gatedlatch and D ip op 267 this, consider the sequential system with state description s(t + 1) = s(t) x(t) whose implementation is depicted in Figure 8.9a. If the clock pulse is narrow (smaller than the delay of the gatedlatch), the system operates correctly as indicated in the timing diagram depicted in Figure 8.9b. The state changes at most once per clock pulse, and the system behavior corresponds to the statetransition function described above. On the other hand, if the width of the clock pulse is larger than the gatedlatch delay, then the operation is as indicated in Figure 8.9c. The new value of the state is fed back to the gatedlatch input while the clock signal is still 1, which produces another change of state. The behavior of the system does not correspond to the expected statetransition function. If the clock pulse is even wider, then more than two state changes could occur. This behavior of multiple state changes per clock pulse is called a race condition, and must be avoided for correct operation. Example 8.2 If the minimumpropagation delay of the xor gate in Figure 8.9a is 1.5 ns] and the minimum propagation delay of the latch is 1.2 ns], then the maximum width of the clock pulse to avoid races is 2.7 ns]. Consequently, the correct behavior of a synchronous sequential network depends on the relative values of the pulse width and the gatedlatch delay. The desired values of these parameters con ict: small gatedlatch delays are desirable for fast network operation, but very narrow clock pulses are not easily realizable. Moreover, the gatedlatch delay and the clock width might have variations during the operation of the system. Thus, a gatedlatch as the binary cell of a synchronous sequential system does not lead to reliable operation, so that other type of cells must be used. The solution to the above mentioned problem consists in using an edgetriggered cell (also called edgesensitive cell, in contrast to the levelsensitive cell considered before). In this new cell, loading of a new state is caused (triggered) by the transition (edge) of the clock signal instead of by its value (level). Edgetriggered cell As shown in Figure 8.10, two types of edgetriggered cells exist, depending on which edge produces the state change: Leadingedgetriggered cell (also called positiveedge triggered). The triggering transition is the rst (rising) edge of the pulse, when the clock changes from 0 to 1. Trailingedgetriggered cell (also called negativeedge triggered). The transition occurs at the second (falling) edge, when the clock changes from 1 to 0. 268 Chapter 8. Sequential networks CLK x t y
p x Y D y Q CLK E z Y t XOR t XOR (b) CLK (a) x t y
p t p Y t XOR t t
XOR XOR (c) Figure 8.9: a) Sequential network. b) Correct timing behavior. c) Incorrect timing
behavior. 8.3. Gatedlatch and D ip op
Input D Output Q CLK (a) Triggering edge CLK CLK CLK (b) Triggering edge Q Input D Output 269 x tp y x tp y Y Y (c) (d) Figure 8.10: Edgetriggered cell: a) Leadingedgetriggered cell. b) Trailingedge triggered cell. c) Leadingedgetriggered cell in network of Figure 8.9. d) Trailingedgetriggered cell in network of Figure 8.9. Since there is only one edge of each type per clock pulse, this type of operation assures that at most one change of state occurs per clock cycle. Figure 8.10 illustrates the convention used for designating both types of edgetriggered cells, and the timing diagram for the network depicted in Figure 8.9 when an edgetriggered cell is used. Masterslave implementation Edgetriggered cells can be implemented with a masterslave structure, which consists of two gatedlatches as shown in Figure 8.11a.2 The clock signal is connected to input E of the rst latch (called the master) so that its output follows the input to the cell while the clock signal has value 1, and does not change when the clock has value 0. In contrast, the complement of the clock is connected to input E of the second latch (called the slave) so that its output 2 Some TTLoriented texts make a distinction among a masterslave cell and an edgetriggered cell. However, since the behavior is the same and the masterslave implementation is used in cmos, we do not make such a distinction. 270 Chapter 8. Sequential networks follows its input (which corresponds to the output of the master cell) while the clock has value 0, and does not change when the clock has value 1. As shown in Figure 8.11b, the input to the masterslave cell is loaded into the master cell during the clock pulse, and is transferred to the slave cell after the clock pulse has terminated. This assures that the change of state (output S ) occurs when the clock changes from 1 to 0, so the cell is trailingedge triggered. As a followon to the discussion above, a leadingedgetriggered cell is obtained by connecting the complemented clock signal to the master cell and the uncomplemented clock signal to the slave cell. The edgetriggered binary cell just presented is called a D ip op. As shown in Figure 8.12, the D ip op has one input called D (data) and two outputs corresponding to the state (Q) and its complement (Q0 ). The complement output is optional. When Q = 1 the ip op is said to be in the \one" or \set" state; similarly, when Q = 0 it is in the \zero" or \reset" state. An additional input, called CLK, receives the clock signal. The transition function of a D ip op is PS = Q(t) D(t) 0 1 0 0 1 1 0 1 NS = Q(t + 1) That is, the next state Q(t + 1) corresponds to the value of the input D(t). Thus, the D ip op is called a \delay" ip op. Equivalently, the operation can be described by the characteristic expression: Q(t + 1) = D(t) or by the state diagram shown in Figure 8.12. Note that the binary cells of the state register in the canonical implementation (see Figure 8.4) precisely correspond to D ip ops. A D ip op may also have \asynchronous" inputs, usually labeled PR (preset) and CLR (clear), which are used to force the ip op into the 1 or 0 state, respectively, independent of other inputs and the clock. Preset and clear are used to initialize ip ops at the beginning of the system operation. Since we are concerned with synchronous sequential systems, we will not include preset and clear inputs in logic diagrams and textual speci cations. We now discuss some basic timing parameters of binary cells. More speci cally, we consider a leadingedge triggered cell in which the change of state is caused D ip op Timing parameters of a binary cell 8.3. Gatedlatch and D ip op 271
W S Input I D Q D Q Output CLK E Master cell E Slave cell CLK’ (a) CLK I W CLK’ S t
p t p W latched (b) S latched Figure 8.11: a) Masterslave implementation of trailingedgetriggered cell. b)
Masterslave state change process. PR (preset) INPUT D(t) CLK 1 OUTPUTS 0 Q=0 0 Q=1 1 DQ Q’ Q(t) Q’(t) (optional) CLR (clear) Figure 8.12: D ip op and its state diagram. 272
CLK setup time
Input
D Q CLK Chapter 8. Sequential networks
tw t su th hold time State Input State tp propagation delay Figure 8.13: Time behavior of cell. by the leading edge of the clock pulse. With respect to this synchronizing event, the following timing parameters are de ned (see Figure 8.13): Setup time (tsu) is the minimum time interval from the stabilization of the
cell input to the triggering edge of the clock. Hold time (th ) is the minimum time interval from the triggering edge of the
clock to a subsequent change in the input to the cell. Pulse width (tw ) is the minimum width of the synchronizing clock pulse. Propagation delay (tp) is the time interval from the triggering edge of the clock to the stabilization of the new state (cell output). When appropriate, we distinguish lowtohigh (tpLH ) and hightolow (tpHL ) propagation delays. As for gates, the propagation delay depends on the load connected to the cell output. The characteristics of a cmos D ip op (of the same family as the gates of Chapter 3) are shown in Table 8.1. In addition to the timing characteristics, the load factor and the size of the module are given; these are de ned in the same manner as for gates. 8.4 Timing characteristics of sequential networks
We now determine the timing parameters of a sequential network in the canonical implementation, in terms of the timing parameters of the binary cells and 8.4. Timing characteristics of sequential networks 273 Table 8.1: Characteristics of a cmos D ip op Input Size factor tpLH tpHL tsu th tw std. equiv. ns] ns] ns] ns] ns] loads] gates] 0:49 + 0:038L 0:54 + 0:019L 0:30 0:14 0.2 1 6 L: output load of the ip op This ip op has only the uncomplemented output the delays of the associated combinational networks. For simplicity, we consider a Mooretype sequential network; the extension to a Mealytype network is straightforward. Figure 8.14 depicts a canonical network in which d1x and d1y are the delays of combinational network C 1 with respect to input x and to the feedback input from the state register y, respectively. Moreover, d2 is the delay of the output network C 2. Then, the following relationships hold: Network setup time. As illustrated in Figure 8.14b, the cell setup time restriction requires that the input to the cell be stable at t . Since the cell input corresponds to the output from network C 1, which has a delay d1x, the input x to the network must be stable that much earlier. That is, tx (net) = d1x + tsu(cell) su Delays Network hold time. Since the network input x changes a time interval d1x before the cell input Y , it would seem that the network hold time should be th (cell) d1x. However, d1x is the maximum delay between the stabilization of x and that of Y , but Y might begin to change earlier, as shown by the shaded interval in Figure 8.14c. Since usually the minimum time for which the output of C 1 remains stable after input x changes is not known, we assume that this time is 0; therefore, the hold time of the network is equal to the hold time of the cell. That is, th (net) = th (cell) Network propagation delay. Since network C 2 has delay d2, the network output stabilizes d2 time units after a change in the output of the cell. That is, tp (net) = tp (cell) + d2 274 Chapter 8. Sequential networks t*
y delay d1 CLK State Register Y z
C2 y x C1 Network input x Cell input
t su (cell) x delay d1 delay d2
CLK C1 delay d1x (b)
t
su (net) Cell setup time Network setup time (a) CLK CLK Network input x
d1
x Cell output t p (cell) d2 Cell input
t h (cell) (c) Cell hold time Network output z
(d) t p (net) t h (net) Network hold time Figure 8.14: Timing factors in sequential networks: a) The network. b) Network
setup time. c) Network hold time. d) Network propagation delay. 8.4. Timing characteristics of sequential networks 275 Maximum clock frequency. Another important timing parameter of a se quential system is the minimum clock period (or its inverse, the maximum clock frequency) because it determines the speed at which the system operates. The determination of this minimumperiod requires considering all the delays that occur in a clock cycle, as shown by the timing diagram in Figure 8.15a. In addition to those discussed earlier, these delays include: tin, which is the time between the triggering edge of the clock and the stabilization of input x; and tout , which is the time between the stabilization of output z and the next clock triggering edge. In a completely synchronous system, input x is produced by the output of another sequential module (see Figure 8.15b), so that tin is the propagation delay of the module producing x (i.e., tin = tp (A)). Similarly, output z is the input to another sequential module, so that tout = tsu(B ) is the setup time of this module. In terms of the parameters de ned above, the minimum clock period Tmin = 1=fmax is (see Figure 8.15c) Tmin = max (tin + tx (net)); (tp (cell) + ty (net)); (tp (net) + tout)] su su The derivation of this expression assumes that th (cell) tp (cell). Substituting, we get the following expression in terms of the characteristics of the cell Tmin = max (tin + d1x + tsu(cell)); (tp (cell) + d1y + tsu(cell)); (tp (cell) + d2 + tout )] ical network in which the propagation delays of the input and output networks are d1x = d1y = 2:5 ns] and d2 = 3 ns], respectively. The setup time of the register cells is tsu = 0:3 ns], and the propagation delay is tp = 1 ns]. The network input stabilizes no later than tin = 2 ns] after the triggering edge of the clock; the output needs to be stable for tout = 3 ns] before the next triggering edge. The minimum clock period is Tmin = max (2 + 2:5 + 0:3); (1 + 2:5 + 0:3); (1 + 3 + 3)] = 7 ns] and the maximum frequency is fmax = 7 1 0 9 140 MHz] 1 Example 8.3 Determine the maximumclock frequency for a Moore canon 276 Chapter 8. Sequential networks CLK t in = t p (A) t
p x y Y z t + d2 p t su (cell) tout = tsu (B) (a)
System S delay d1 y State Register Y System A z
C2 y System B x C1 x delay d1 delay d2 CLK CLK CLK (b) CLK With respect to network input x With respect to state register output y With respect to network output z
t
p d1 x t su t in = t p (System A) d1 y t su tout = tsu (System B) tp d2 Minimum clock period
(c) Figure 8.15: Maximum clock frequency: a) Clock period and signal delays. b) The
network. c) Minimum clock period. 8.5. Analysis of canonical sequential networks 277 Clock skew. For synchronous operation, all cells of a network should receive the triggering edge of the clock at the same time. As illustrated in Figure 8.16b, incorrect operation occurs if one cell receives the edge, changes state, and the change propagates to the input of another cell before that cell receives its triggering edge. On the other hand, due to the delay produced by the lines that carry the clock and the bu ers required to restore the clock shape, it is not possible to assure that the triggering edge is received exactly at the same time by all cells. The time di erence between the instants that the triggering edge is received by two cells is called the clock skew between these two cells. As indicated, clock skew between any pair of cells has to be limited for correct operation. This problem is aggravated for larger networks, in which the distance between cells is larger, and for highspeed systems, in which the propagation of signals is fast. Special clock distribution networks are used to limit clock skew. 8.5 Analysis of canonical sequential networks
Let us now focus our attention on the analysis of canonical sequential networks, that is, in determining a speci cation of the system implemented by a network. In this case, the functional analysis consists of the following steps: 1. Analyze the combinational network to determine the transition and output functions, using the procedures described in Chapter 4. 2. Determine a suitable highlevel speci cation of the transition and output functions. 3. If desired (or required), determine a description of the time behavior of the system. In addition, the analysis also produces other characteristics of the network, such as the load factor and size (as discussed in Chapter 4), and the timing characteristics, as described in the previous section. Example 8.4 Analyze the synchronous sequential network depicted in Fig ure 8.17. This network consists of a twocell state register and combinational logic. Representing the present state by the vector (y1 ; y0 ) and the next state by the vector (Y1 ; Y0), the analysis of the combinational network produces the following expressions for the statetransition and output functions: 278 Chapter 8. Sequential networks CLK x DQ FF1 Q1 delay
CLK* Q2 DQ FF2 z CLK x Q1 Q2 (a)
CLK x Q1
CLK* Q2 clock skew (b) Figure 8.16: a) Network behavior without clock skew. b) Network behavior with
inadmissible clock skew. 8.5. Analysis of canonical sequential networks
x’ y1 ’ y0 ’ y0 ’ y0 ’ y0 FF1 y0 CLK y 1 = z0 ’ Y1 Y0 DQ FF0 y0 = z1 y0 ’ 279 x y1 ’ y1 y1 y1 ’ DQ y1 Figure 8.17: Sequential network in Example 8.4. State transition Output
0 0 Y0 = x0y1 xy0 0 0 0 y1 x0y0 y1 xy0 y1 x0y0 y1 0 Y1 = xy0 0 z0 = y1 z1 = y0 These functions are also described by the following table, obtained by evaluating expressions for Y1 and Y0 for all combinations of y1 , y0 and x (z1 and z0 obtained similarly): PS Input y1 y0 x = 0 x = 1 00 01 11 01 01 11 00 11 10 10 01 00 11 00 10 10 Y1 Y0 z1 z0 NS Output To obtain a highlevel description, let us de ne the following codes: xx z1 z0 z y1 y0 s 0a 00 c 00 S0 01 d 01 S1 1b 10 e 10 S2 11 f 11 S3 Using these codes, and assuming that the initial state is S2 , the highlevel speci cation of the system is 280 Chapter 8. Sequential networks
a S0 /d b a S2 /c b a b a b S1 /f S3 /e (a)
x(t) s(t) z (t) a S2 c a S2 c b S2 c a S1 f b S3 e b S2 c a S1 f
(b) b S3 e a S2 c a S2 c b S2 c b S1 f b S0 d a S3 e S0 d Figure 8.18: a) State diagram for sequential network. b) A sequence of inputoutput pairs. Input: Output: State: Initial state: Functions: x(t) 2 fa; bg z (t) 2 fc; d; e; f g s(t) 2 fS0 ; S1 ; S2; S3 g s(0) = S2 The statetransition and output functions are PS x(t) = a x(t) = b S0 S1 S3 d S1 S3 S0 f S2 S2 S1 c S3 S0 S2 e NS z (t) The corresponding state diagram and a sequence of inputoutput pairs are shown in Figure 8.18. 8.6. Design of canonical sequential networks 281 Assuming gates and D ip ops of the family described in Table 4.1 and Table 8.1, the following characteristics are obtained. We consider the case when x changes from 0 to 1 and z0 changes from 1 to 0; the other cases are calculated in a similar manner. The critical path for the setup time is through gates not, and3, and or4. Input load factors: Lx = 4 Setup time: tsu(net) = tpHL (not) + tpHL (and3) +tpHL (or4) + tsu = (0:05 + 0:017 3) + (0:18 + 0:018) +(0:45 + 0:025) + 0:3 = 1:07 ns] Hold time: th (net) = 0:14 ns] Propagation delay: tp (z0 ) = tpLH (ff) + tpHL (not) = (0:49 + 0:038 3) +(0:05 + 0:017 (L + 3)) = 0:70 + 0:017L ns] (load of not is L + 3, load of ip op is 3) Size: = 6 2+2+3+2 6+3 1 = 32 equivalent gates. 8.6 Design of canonical sequential networks
The design of a canonical sequential network, which requires the state description of the system, consists of the following steps: 1. Transform the transition and output functions into a form suitable for implementation. For example, if these functions are speci ed by means of a state diagram, transform them into highlevel expressions or state tables. 2. Specify a state register to encode the required number of states. 3. Design the required combinational network. If the design is done at a high level, the highlevel descriptions can be used directly. On the other hand, if the design is done at the binary level, then it is necessary to select codes for the input, output, and state, and transform the highlevel description of the functions into descriptions by switching functions (tables, expressions, or maps). In either case, the design of the combinational network uses the methods described in Chapters 4, 5 and 6. This procedure is illustrated in the following example. 282 having the following speci cation: Input: x(t) 2 fa; b; cg Output: z (t) 2 f0; 1g State: s(t) 2 fA; B; C; Dg Initial state: s(0) = A Functions: PS Chapter 8. Sequential networks Example 8.5 Design a binarylevel sequential network to implement a system The statetransition and output functions are Input x=a x=b x=c A C ,0 B ,1 B ,0 B D,0 B ,0 A,1 C A,0 D,1 D,0 D B ,0 A,0 D,1 NS; z In this case, the system is speci ed by a state table, so that step 1 in the procedure above is not required. Since there are four states, we need a state register with two cells. Let us select the following codes for the input and the state (the output is already coded): Input code x x1 x0 a01 b10 c11 are State code s y1 y0 A00 B10 C01 D11 With these codings, the corresponding statetransition and output functions PS y1 y0 00 10 01 11 01 01,0 11,0 00,0 10,0 x1x0 10 11 10,1 10,0 10,0 00,1 11,1 11,0 00,0 11,1 Y1 Y0; z NS , Output Note that the combination x1x0 = 00 never appears, so it is considered a \don't care" case. From this table, we obtain the Karnaugh maps shown bellow. The process is straightforward: a combination of (y1 ; y0; x1; x0) = j 8.6. Design of canonical sequential networks
y
1 283 x’ 1 y’ 1 x 1 y’ x’ x
0 0 Y 1 DQ FF1 y 0 1 1 y’ y
1 x 0 0 y’ x’ y
0 1 Y 0 y’ x x’ y’
0 DQ FF0
CLK y 0 0 1 1 1 y’ y x 1 0 z 1 x Figure 8.19: Sequential network in Example 8.7. corresponds to cell j on the Kmaps; the cell entries on the Kmaps for Y1, Y0 and z are Y1 (j ), Y0 (j ) and z (j ), respectively. x0 x0 x0 z: Y1 : Y0 : 011 100 001 011 011 001 y0 y0 y0 110 010 010 y1 y1 y1 101 100 010 x1 x1 x1 From these maps, we obtain the following sumofproducts expressions:
0 0 Y1 = y1 x1 y1 x01 + y0 x00 y0 x1x0 0 0 Y0 = y0 x01 y1 y0 x1 y0 x1x0 0 z = y1 x00 y1 x1x0 The sequential network, consisting of a twolevel gate network and a twocell state register, is shown in Figure 8.19. 284
PR (preset) Chapter 8. Sequential networks 10 0Q=0 01 Q=1 0 S
CLK Q Q(t) R Q’ Q’(t) (optional) CLR (clear) Figure 8.20: SR ip op and its state diagram. 8.7 Other ip op modules: SR, JK, and T
We now discuss the logical de nitions of three other ip ops. Implementations of these ip ops are provided in some families, and can be used instead of D ip ops to reduce the complexity of the combinational part of a sequential network. SR (SetReset) ip op The SetReset ip op has two inputs, as indicated in Figure 8.20. Its transition function is PS = Q(t) S (t)R(t) 00 01 10 11 0 0011 101NS = Q(t + 1) In words, the ip op is set (Q(t + 1) = 1) if S (t) = 1 and R(t) = 0; it is reset (Q(t + 1) = 0) if S (t) = 0 and R(t) = 1; it does not change state when S (t) = 0 and R(t) = 0; and the combination S (t) = 1, R(t) = 1 is not allowed. The corresponding characteristic expression, obtained from a Kmap, is Q(t + 1) = Q(t)R0 (t) S (t) R(t) S (t) = 0 The corresponding state diagram is also shown in Figure 8.20. with the restriction that JK ip op The JK ip op, shown in Figure 8.21, is a variation of the setreset ip op. The transition function is 8.8. Analysis of networks with ip ops
PR (preset) 285
1 J
CLK Q Q(t) 0Q=0 1 Q=1 0 K Q’ Q’(t) (optional) CLR (clear) Figure 8.21: JK ip op and its state diagram. J (t)K (t) 00 01 10 11 0 0011 1 1010 NS = Q(t + 1) The operation is the same as for the SR ip op, except that the combination J (t) = 1, K (t) = 1 is allowed and produces a change of state. The characteristic expression is Q(t + 1) = Q(t)K 0 (t) Q0 (t)J (t) The T ip op, shown in Figure 8.22, has only one input called T . It remains in the same state if T = 0 and changes state if T = 1. The transition function is PS = Q(t) T (t) 0 1 0 0 1 1 1 0 NS = Q(t + 1) The characteristic expression is Q(t + 1) = Q(t) T (t) One type of ip op can be implemented using another type and a combinational network. For example, Figure 8.23 illustrates the implementation of a T ip op using a JK ip op. PS = Q(t) T (Toggle) ip op 8.8 Analysis of networks with ip ops 286
PR (preset) Chapter 8. Sequential networks
1 0 CLK Q=0 1 Q=1 0 T Q Q’ Q(t) Q’(t) (optional) CLR (clear) Figure 8.22: T ip op and its state diagram. T J K Q Q(t) CLK Figure 8.23: T ip op implemented with a JK ip op. The procedure to analyze synchronous sequential networks with ip ops is a generalization of the procedure for canonical networks. The functional analysis is performed as follows: 1. Obtain the transition function of the network by the following twostep process: (a) Determine the inputs to the ip ops in terms of the present state and the inputs to the network. This requires the analysis of the corresponding combinational network. (b) Use the transition function of the ip ops to determine the next state. This twostep process can be performed using tables, diagrams, or expressions. 2. Obtain the output function by analyzing the corresponding combinational network. 3. Determine a suitable highlevel speci cation of the transition and output functions. 8.8. Analysis of networks with ip ops 287 Table 8.2: Characteristics of a family of cmos ip ops FF type Input Size factor tpLH tpHL tsu th tw std. equiv. ns] ns] ns] ns] ns] loads] gates] D 0:49 + 0:038L 0:54 + 0:019L 0:30 0:14 0:20 1 6 JK 0:45 + 0:038L 0:47 + 0:022L 0:41 0:23 0:20 1 8 L: output load of the ip op These ip ops have only uncomplemented outputs Delays x1 Q T B Q A Q’ Q A Q’ A x0
Q
A T Q B Q’ B Q’ Q B z CLK x1 Figure 8.24: Sequential network for Example 8.6. In addition to the functional analysis, other characteristics such as timing and size might be required. The process to determine the timing characteristics is similar to that for the canonical implementation. For the size of the network, it is necessary to add the size of all gates and ip ops. The characteristics of ip ops of the same family as the gates described in Chapter 3 are given in Table 8.2. Note that this family does not include SR nor T ip ops. Example 8.6 Analyze the network given in Figure 8.24. The network has two T ip ops, so that the state variables are QA and QB . The expressions for the ip op inputs are TA = x1QB TB = x0QA 288 Chapter 8. Sequential networks Let us use expressions for the description. Since the characteristic expression for T ip ops is Q(t + 1) = Q(t) T (t), the transition function is represented by QA (t + 1) = QA (t) x1QB (t) QB (t + 1) = QB (t) x0 QA(t) and the output expression is z (t) = x1 (t)Q0B (t) Using these expressions, we obtain the transition and output tables as follows: PS Input Input QAQB x1 x0 x1 x0 00 01 10 11 00 01 10 11 00 00 00 00 00 0 0 1 1 01 01 01 11 11 0 0 0 0 10 10 11 10 11 0 0 1 1 11 11 10 01 00 0 0 0 0 QA QB z NS Output Using the following state assignment and input code QA QB s x1 x0 x 0 0 S0 00a 0 1 S1 01b 1 0 S2 10c 1 1 S3 11d the highlevel speci cation of the system is Input: x(t) 2 fa; b; c; dg Output: z (t) 2 f0; 1g State: s(t) 2 fS0 ; S1 ; S2; S3 g Initial state: s(0) = S0 Functions: The statetransition and output functions are PS S0 S1 S2 S3 a S0 S1 S2 S3 x bc S0 S0 S1 S3 S3 S2 S2 S1 NS d S0 S3 S3 S0 a 0 0 0 0 b 0 0 0 0 x c 1 0 1 0 d 1 0 1 0 z 8.8. Analysis of networks with ip ops
Q Q’
A 289 x A B Q’ J A
Q CLK Q
A B Q Q A K
Q’
B z J B K Q Q B Q’ A Figure 8.25: Sequential network for Example 8.7. Example 8.7 Obtain a highlevel description of the sequential network shown
in Figure 8.25. The network has two JK ip ops (A and B ) so that there are two state variables QA and QB . From an analysis of the combinational network, the ip op input functions are described by the following switching expressions: JA = x0Q0B xQA JB = QA In addition, the output function is z = QA Q0B The transition function is obtained from the JK ip op characteristic expression: 0 QA (t + 1) = QAKA + Q0AJA 0B + Q0A(x0 Q0B + xQA ) = QAQ = Q0B (QA + x0)
0 QB (t + 1) = QB KB + Q0B JB = QB (x + QA) + Q0B QA = QB x + QA KA = QB KB = x0Q0A resulting in the following table: 290 PS QA QB 00 01 10 11 Chapter 8. Sequential networks NS Output x=0 x=1 z QA QB QA QB 10 00 1 00 01 0 11 11 1 01 01 1 The output function, also shown in the table, is obtained directly as a function of the present state. To obtain a highlevel description, let us assign state symbols as follows QA QB 00 01 10 11 S S0 S1 S2 S3 The corresponding highlevel speci cation is Input: Output: State: Initial state: Functions: x(t) 2 f0; 1g z (t) 2 f0; 1g s(t) 2 fS0 ; S1 ; S2; S3 g s(0) = S0 The statetransition and output functions are PS S0 S1 S2 S3 Input x=0 x=1 S2 S0 S0 S1 S3 S3 S1 S1 NS 1 0 1 1 z These functions are depicted in the state diagram shown in Figure 8.26. Using the family of gates and ip ops described in Table 4.1 and Table 8.2, the following characteristics are obtained. We consider the case in which x changes from 1 to 0 and z changes from 0 to 1; the analysis of the other cases is similar. The critical path for the setup time is through gates not, and, and or. 8.9. Design of networks with ip ops
1 0 1 S1 /0 S0 /1 0 S2 /1 0,1 0,1 S3 /1 291 Figure 8.26: State diagram in Example 8.7. Lx = 2 tsu (net) = tpLH (not) + tpLH (and) + tpLH (or) +tsu (FF ) = (0:02 + 0:038 2) + (0:15 + 0:037) +(0:12 + 0:037) + 0:41 = 0:85 ns] Hold time: th (net) = 0:23 ns] Propagation delay: tp (net) = tpHL (ff) + tpLH (not) + tpLH (or) = (0:47 + 0:022 2) + (0:02 + 0:038 2) +(0:12 + 0:037L) = 0:73 + 0:037L ns] Size: = 3+2 5+8 2 = 29 equivalent gates Input load factor: Setup time: 8.9 Design of networks with ip ops
The procedure for the design of ip op networks is a generalization of the one used for the canonical implementation at the binary level. The main di erence is that, while in the canonical case the input to each D ip op corresponds directly to the component of the next state, the input to other ip op types are designed to produce the desired transitions. The input values required for particular transitions depend on the type of ip op. The corresponding function indicating the ip op inputs required for each transition is called the excitation function E (Q(t); Q(t + 1)). We now describe how to obtain the excitation function for the SR ip op, and then give this function for the other ip ops. For the SR ip op, a transition from Q(t) = 0 to Q(t + 1) = 0 requires S (t) = 0; R(t) = 0 (no change), or S (t) = 0; R(t) = 1 (reset). Consequently, this transition requires S (t) = 0 and R(t) = dc. Similarly, 292 Chapter 8. Sequential networks for to inputs should be Q(t) = 0 Q(t + 1) = 1 S (t) = 1, R(t) = 0 Q(t) = 1 Q(t + 1) = 0 S (t) = 0, R(t) = 1 Q(t) = 1 Q(t + 1) = 1 S (t) = dc, R(t) = 0 Following a similar procedure, we obtain the excitation functions for the four types of ip ops being considered: D ip op
0 0 0 NS D(t) SR ip op
0 1 PS 0 1 1 1 1 PS NS 01 0 10 01 0 S (t)R(t) D(t) = Q(t + 1) JK ip op
PS 0 1 NS 0 1 011 0 J (t)K (t) PS 0 1 T ip op
0 0 1 NS T (t) 1 1 0 T (t) = Q(t) Q(t + 1) Note that, in order to exploit the \don't cares," it is not suitable to use expressions for the SR and JK ip ops. The procedure for the design of ip op networks consists of the following steps: 1. Obtain a binary description of the system. This step is performed by selecting codes for the input, output and state, and transforming the statetransition and output functions into the corresponding set of switching functions. 2. Select the type of ip op used to store the statevector. In most cases all ip ops in a network are of the same type, but the procedure can also be applied to the case in which several types of ip ops are used. 3. Use the transition function of the system to determine the inputs to the ip ops required to produce the desired transitions. For this step, use the excitation function of the ip op. 8.9. Design of networks with ip ops
x=0 S0 /0 x=1 0 S1 /1 1 0 S2 /2 1 1 0 S3 /3 1 0 S4 /4 293 Figure 8.27: State diagram for Example 8.8. 4. Design a combinational network to produce these ip op inputs in terms of the present state and the network inputs. The following examples illustrate this procedure. Example 8.8 Using T ip ops, design a modulo5 counter whose speci cation is as follows: Input: x(t) 2 f0; 1g Output: z (t) 2 f0; 1; 2; 3; 4g State: s(t) 2 fS0 ; S1 ; S2; S3 ; S4g Initial state: s(0) = S0 The system counts modulo5 the number of 1's in the input sequence (i.e., it counts 0,1,2,3,4,0,1,2,3,4,0...), as depicted in the state diagram shown in Figure 8.27. We begin the design by coding the input, output, and state sets. Since the input is a binary variable, it is already coded. The output set requires at least three binary variables. One possibility is to code the values of z by their representations in a radix2 number system, as follows: z z2 z1 z0 0000 1001 2010 3011 4100 Since there are ve states, at least three binary variables are required to code the state. To simplify the output network, we use the same code for the state and the output vector, so that (z2 ; z1 ; z0) = (Q2 ; Q1; Q0). With these codes, the statetransition table and the ip op input functions are Functions: 294 Chapter 8. Sequential networks PS Input Input Q2Q1 Q0 x = 0 x = 1 x = 0 x = 1 000 000 001 000 001 001 001 010 000 011 010 010 011 000 001 011 011 100 000 111 100 100 000 000 100 NS T2 T1 T0 The functions for the ip op inputs T2 , T1 , and T0 are obtained from the excitation function of a T ip op (namely, T = Q(t) Q(t +1)) and the statetransition table. For example, when PS = (0; 0; 0) and x(t) = 0, then Q0 (t) = 0 and Q0(t +1) = 0 so that T0 (t) = 0; similarly, when PS = (0; 0; 0) and x(t) = 1 then Q0 (t) = 0 and Q0 (t + 1) = 1 so that T0 (t) = 1. The corresponding switching functions are described by the following Karnaugh maps: x x x T2 : T1 : T0 : 0000 0010 0110 0010 0010 0110 Q1 Q1 Q1 Q2 Q2 Q2 010000Q0 Q0 Q0 From these maps, we obtain the input expressions T2 = xQ2 xQ1 Q0 T1 = xQ0 T0 = xQ02 The resulting sequential network is shown in Figure 8.28. Example 8.9 Using SR ip ops, design a network for a system which has the
following highlevel description: 8.9. Design of networks with ip ops
Q
2 295
T x
Q
1Q 0 2 Q T Q
FF2 2 z2 Q’ Q’
T Q 2 Q 0 1 T Q
FF1 1 z1 Q’
T Q’
2 0 Q T Q
FF0 0 z0 Q’
CLK Figure 8.28: Sequential network in Example 8.8. Input: Output: State: Initial state: Functions: x(t) = (x1 ; x0); xi 2 f0; 1g z (t) 2 f0; 1g s(t) 2 fa; b; c; dg s(0) = a The transition and output functions are PS 01 b,0 a,0 d,0 c,0 x1 x0 10 11 a c,1 c,0 b d,1 d,0 c c,0 a,1 a,0 d,1 d NS; z The input and output are already coded on binary variables. Note that the combination (x1; x0) = (0; 0) is not present, so it is considered a \don't care" case. Two ip ops are needed to store the state, and a possible state assignment is State Q1 Q0 a 00 b 01 c 10 d 11 Consequently, the transition function becomes 296 PS Q1 Q0 00 01 10 11 01 01 00 11 10 Chapter 8. Sequential networks x1 x0 10 11 10 10 11 11 10 00 00 11 NS The required input functions are obtained from the transition function and the excitation function of the SR ip op. As a reminder, this excitation function is Q(t) Q(t + 1) S R 0 0 00 1 10 1 0 01 1 1 0 Now we can obtain the ip op inputs and represent them in Kmaps. As an illustration of the way the entries in the maps are generated, consider the case Q1(t) = 0, Q0(t) = 1, x1 = 0, x0 = 1. For this case the next state is Q1(t +1) = 0, Q0 (t +1) = 0. From the excitation table we get S1 = 0, R1 = , S0 = 0, and R0 = 1, as shown in the corresponding Kmap cell. Consequently, the input functions are: x0 x0 S1 : R1 : 011 00 011 00 Q0 Q 0 001 0 Q1 Q1 0010 x x x0 1 x0 1 S0 : R0 : 100 00100 Q0 Q0 00 101 Q1 Q1 100 0x1 x1 From the maps, we obtain the expressions for the ip op inputs as follows: S1 = x1 Q01 8.9. Design of networks with ip ops
1 Q’ 297
S1 Q x x’
Q S R Q Q’ 0 1 1 FF1 Q’
1 1Q 0 x
Q
1 x 0 1
0 R1 Q’ x’ 1
Q’ CLK S0 S R Q FF0 Q’ Q x’ 1
Q 0 0 x’ 0
Q 0 Q’ 0 R0 1 0 Q’ x’ x0 1 x1 z Q 1 Figure 8.29: Sequential network in Example 8.9. R1 = x00 Q1Q0 x1x0Q1 Q00 S0 = x01 Q00 R0 = x01 Q0 x00 Q1 The Karnaugh map for the output is x0 z: 00 00 01 Q1 01 The output expression is x1 z = x00 Q01 x1x0 Q1 The resulting sequential network is shown in Figure 8.29. 1 1 Q0 0 0 298 Chapter 8. Sequential networks
start start’ "Wait" state S0 start DQ S0
Q’ DQ S1 S1
Q’ DQ S2 S2
Q’ Initially, S 0 is set to 1 and all other flipflops to 0 (preset and clear signals not shown) DQ S3 S3
Q’ DQ S4
CLK S4
Q’ (a) (b) Figure 8.30: One ip op per state approach: a) State diagram. b) Implementation
(outputs omitted). 8.10 Design using special state assignments
The coding of states on binary variables (state assignment) a ects the complexity of an implementation as well as the design process. We discuss two state assignment approaches that, when applicable, greatly simplify the design. One ip opperstate
If the number of states is small, sequential networks with one ip op per state result in straightforward correspondence among state diagram and implementation. As an example, Figure 8.30 shows the state diagram and implementation of the autonomous controller presented in Section 6.6. Note that only one ip op is in state 1 at any time, whereas all others are in state 0; thus, this implementation is also called a onehot approach. The system is initialized by setting to 1 the ip op corresponding to the initial state. 8.11. Description of ip ops and sequential networks in vhdl 299 We now discuss the correspondence among the state diagram and the onehot implementation. The simplest case is a state with one predecessor and one successor, as shown in Figure 8.31a; the corresponding implementation is given in Figure 8.31a'. In the more general case, a state has several predecessors and several successors, and a particular successor is chosen by input values. This situation is shown in Figure 8.31b and the corresponding implementation in Figure 8.31b'. Figure 8.32 illustrates the onehot implementation of a controller for the simple vending machine considered in Section 6.6. Shifting State Register Implementations with a shifting state register are especially suitable for nitememory sequential systems. As discussed in Section 6.5, the (not necessary minimum) state in such a system corresponds to the last m 1 inputs. Consequently, these inputs can be stored in a register and shifted one position each clock cycle, as shown in Figure 8.33; note the implementation of the shift register with D ip ops. Example 8.10 Obtain an implementation using D ip ops of a sequential
system having the following time behavior: Input: x(t) 2 f0; 1g Output: z (t) 2 f0; 1g Function: z (t) = 1 if x(t 3; t) = 1101 0 otherwise Figure 8.33 illustrates an implementation with a state register consisting of three D ip ops, connected so that at time t they contain x(t 3; t 1); that is, the last three inputs represent the state. The output z (t) is obtained using a 4input and gate connected to the state register and the external input. 8.11 Description of ip ops and sequential networks in vhdl
Let us now address the description of ip op modules and their characteristics in vhdl, as well as the description of simple sequential networks using such modules. The description of the function of these basic sequential modules follows the de nitions and examples given in Chapter 7 for sequential systems. However, since the functionality of ip ops is quite simple, the corresponding behavioral descriptions are also quite simple. 300 Chapter 8. Sequential networks Si D Q Si Sj
CLK (a) (a’) Predecessor States D Q Sj Predecessor States D Si
Determined by inputs Successor States inputs CLK Q Si (b) Successor States (b’) Figure 8.31: Primitives for the \one ip opperstate" approach. 8.11. Description of ip ops and sequential networks in vhdl 301 coin . return coin . return "Wait" state S0 coin . return S 5 /return_all_coins, clear_sum S 2 /release_candy, clear_sum change_available S 4 /return_change change_available S3 sum<75 S1 sum=75 sum>75 (a) return
DQ
CLK coin Note: coin . return = 0 S0
Q’
CLK DQ S5
Q’ return_all_coins clear_sum DQ
CLK S2
Q’ release_candy, clear_sum Initially, S 0 is set to 1 and all other flipflops to 0 (preset and clear signals not shown) sum=75 sum>75
CLK DQ S 4 return_change
Q’ DQ
CLK S1
Q’
CLK DQ S3
Q’ sum<75 change_available (b) Figure 8.32: A \one ip opperstate" implementation of a controller for vending machine: a) State diagram. b) Implementation. 302
CLK x(t1) x(t) DQ Q’ DQ Q’ x(t2) Chapter 8. Sequential networks x(t3) DQ Q’ z(t) Figure 8.33: Implementation of pattern recognizer in Example 8.10. In contrast to the descriptions given in Chapter 7, ips ops are controlled by a clock pulse with nonzero width; in particular, ip ops are synchronized with a clock edge. The interpretation of the PROCESS describing the transition function of these modules is triggered by a transition of the clock signal, so the description must detect whether the clock transition is the appropriate one. For this purpose, an IF statement checking for the current value of the clock signal is su cient: in the case of a leadingedge transition, the value of the clock must be 1, whereas in the case of a trailingedge transition the value must be 0. 8.11.1 Description of ip ops Let us rst consider the description of the ip ops in Table 8.2, but assuming constant delay (independent from the transition direction and from the load). Example 8.11 Flip ops with constant delays are described as follows:
USE WORK.BitDefs_pkg.ALL; ENTITY D_flip_flop IS PORT(d : IN BIT; q : OUT BIT; clk : IN BIT); END D_flip_flop; ARCHITECTURE basic OF D_flip_flop IS SIGNAL ds: BIT;  flipflop state BEGIN PROCESS (clk)  transition function CONSTANT delay: TIME := 500 ps; BEGIN IF (clk = '1') THEN 8.11. Description of ip ops and sequential networks in vhdl
ds <= d AFTER delay; END IF; END PROCESS; PROCESS (ds) BEGIN q <= ds; END PROCESS; END basic; USE WORK.BitDefs_pkg.ALL; ENTITY JK_flip_flop IS PORT(j,k : IN BIT; q : OUT BIT; clk : IN BIT); END JK_flip_flop; ARCHITECTURE basic OF JK_flip_flop IS SIGNAL jks: BIT;  flipflop state BEGIN PROCESS (clk)  transition function CONSTANT delay: TIME := 450 ps; VARIABLE jk : BitVector2; BEGIN IF (clk = '1') THEN jk:= j & k; CASE jk IS WHEN "00" => jks <= jks AFTER delay; WHEN "01" => jks <= '0' AFTER delay; WHEN "10" => jks <= '1' AFTER delay; WHEN "11" => jks <= not(jks) AFTER delay; END CASE; END IF; END PROCESS; PROCESS (jks) BEGIN q <= jks; END PROCESS; END basic;  output function  output function 303 These descriptions consist of two processes, one for the state transition function and the other for the output function. The process describing the state transition function contains an IF statement which checks for a leadingedge transition in the clock signal, and the rest of the process gives the functionality of the transition function. In the case of the D ip op, such a functionality 304 Chapter 8. Sequential networks clk J K Q Q’ 1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns Figure 8.34: Timing diagram for JK ip op. consists of latching the data at the d input, whereas in the case of the JK ipop the functionality is described by the body of the CASE statement. Since in both cases the ip op output corresponds to the state, the process describing the output function is just the assignment of the state to the output signal. The state of the ip op is saved in SIGNAL ds and jks, respectively. The propagation delay of the cell is given with respect to the clock edge triggering the transition function; since the output corresponds to the state, there is no delay in the output function. Figure 8.34 depicts a timing diagram for the operation of the JK ip op described above, as obtained from a simulation run. Note that the description of the JK ip op uses the package BitDefs pkg, which contains de nitions for the bitvector TYPEs and functions used throughout this book. This package, which will be used repeatedly in later chapters, is given in Appendix B. As in the case of basic gates, let us now show a re nement of the descriptions in the example above by giving another architecture body for the D ip op, in which there are di erent delays depending on the type of output transition. Example 8.12 The following description corresponds to a D ip op whose transition delay depends on the type of output transition:
ARCHITECTURE delays OF D_flip_flop IS SIGNAL ds: BIT;  state BEGIN PROCESS (clk) CONSTANT TpHL : TIME := 540 ps; CONSTANT TpLH : TIME := 490 ps; VARIABLE ds_d : BitVector2; BEGIN IF (clk = '1') THEN 8.11. Description of ip ops and sequential networks in vhdl
ds_d := ds & d; CASE ds_d IS WHEN "00"  "11" WHEN "10" WHEN "01" END CASE; END IF; END PROCESS; PROCESS (ds) BEGIN q <= ds; END PROCESS; END delays;  previous state and current input => null; => ds <= d AFTER TpHL; => ds <= d AFTER TpLH; 305 In this case, the description uses a variable to momentarily capture the previous state. The propagation delay of the cell depends on the previous and new values of the state, as described by the entries in the CASE statement. Also as in the case of basic combinational gates, the delay of a ip op can be dependent on the load imposed on the module (fanout); the corresponding vhdl description is an extension of the one in the previous example, along the same lines as done for the case of basic gates in Chapter 3, using a GENERIC statement in the entity declaration de ning the load. Similarly, aspects such as input loadfactor, fanout factor, and the size of the ip op (in terms of equivalent gates) are described using ATTRIBUTE statements. Flip op modules have additional timing parameters, namely setup time, holdtime, and clock pulsewidth. These parameters correspond to constraints that must be ful lled to guarantee correct behavior; otherwise, the ip op outputs become unde ned during the interval that the constraints are not ful lled, and these unde ned signals propagate throughout the rest of the network. A complete description of a ip op module would include the generation of such unde ned values, usually represented as 'X', and signals must also support that value (i.e., a multivalued binary signal). The generation of unde ned values in the /uvhdl/ descriptions is beyond the scope of this text; instead, timing parameters are incorporated into the descriptions, and their values are used for verifying that the timing constraints are ful lled during simulation, displaying a warning message when that is not the case. For clarity in the descriptions, timing constraints veri cation is performed in a separate PROCESS. The function NOW, the statement ASSERT, and the signal attribute EVENT are used for these purposes: NOW returns the current simulation time (a value of TYPE TIME). The attribute EVENT, of type BOOLEAN, is de ned for every signal; it has the value TRUE if an event has occurred in the corresponding signal at the current time or FALSE otherwise, as follows: 306
SIGNAL x : BIT; VARIABLE flag: BOOLEAN; flag:= x'EVENT; Chapter 8. Sequential networks This construct checks whether there has been a transition in signal x at the current time, and assigns the value TRUE or FALSE to variable flag accordingly. ASSERT is a reporting mechanism with an associated condition, which has the following structure:
ASSERT(condition) REPORT "report string" SEVERITY level; If the condition speci ed in the ASSERT is FALSE, then the text string that follows the clause REPORT is displayed together with the severity level speci ed in the clause SEVERITY; prede ned severity levels are WARNING and FATAL. (In the case of FATAL, the simulation ends at that point.) Example 8.13 The following description uses vhdl statements which allow reporting the violation of timing constraints:
ARCHITECTURE constraints OF D_flip_flop IS SIGNAL ds: BIT;  state BEGIN PROCESS (clk)  transition function CONSTANT Tp: TIME:= 500 ps;  delay BEGIN IF (clk = '1') THEN ds <= d AFTER Tp; END IF; END PROCESS; PROCESS (ds) BEGIN q <= ds; END PROCESS;  output function PROCESS (clk,d)  timing characteristics CONSTANT Tsu : TIME := 300 ps;  setup time CONSTANT Th : TIME := 140 ps;  hold time CONSTANT Tw : TIME := 200 ps;  clock pulse width VARIABLE d_change : TIME:= 0 ps;  time of last d change VARIABLE clk_ldedge: TIME:= 0 ps;  time of last clk change BEGIN IF (d'EVENT) THEN  EVENT: signal attribute d_change:= NOW;  record instant of d change 8.11. Description of ip ops and sequential networks in vhdl
 verify hold time constraint ASSERT (NOW  clk_ldedge >= Th) REPORT "hold time violation" SEVERITY WARNING; END IF; IF (clk'EVENT) THEN IF (clk = '1') THEN clk_ldedge:= NOW; 307  leading clock edge  record instant of clk change  verify setup time constraint ASSERT (NOW  d_change >= Tsu) REPORT "setup time violation" SEVERITY WARNING; ELSE  trailing clock edge  verify pulse width constraint ASSERT (NOW  clk_ldedge >= Tw) REPORT "pulse width violation" SEVERITY WARNING; END IF; END IF; END PROCESS; END constraints; This description consists of three processes: the rst one describes the transition function and the second describes the output function, as in the previous examples. The third process contains the veri cation of the timing constraints, by keeping track of the instant when the last transition took place in the input and clock signals. So, for example, if input d changes at time 1250 ps, and the clock pulse is received at time 1500 ps, then the condition NOW  d change >= Tsu is false, and the warning is reported. 8.11.2 Description of ip op networks Let us now address the description of ip op networks. Such networks are described at the structural level, that is, by listing the ip ops and combinational modules comprising the network and their interconnection. The functionality and other characteristics of ip ops and gates are described separately, as discussed in previous chapters. As we already know, those descriptions become part of a structural description by declaring the entities used in the network. Example 8.14 We now give the vhdl description of the gate network depicted in Figure 8.35. The description of ip ops and gates has already been discussed; we assume such descriptions are available in the library WORK, so we just use them here. The entity declaration for this network is as follows: 308
1 Q’ Chapter 8. Sequential networks
x
S1 S R R1 Q Q’ FF1 x’ 0
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0 0 U9 U10 CLK S0 S R Q FF0 Q’ Q 0 U3 U4 U5 U11 U6
R0 Q’ 0 x’ 0
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1 x’ 0
Q’ x0 x1
Q 1 z 1 Figure 8.35: Sequential network in Example 8.14.
USE WORK.ALL; ENTITY seq_netw IS PORT(x1,x1p: IN x0,x0p: IN z : OUT clk : IN END seq_netw; BIT; BIT; BIT; BIT); The architecture body lists the modules used in the network and their interconnections. Labeling the modules and signals as depicted in Figure 8.35, we obtain the structural description given in Figure 8.36. 8.12 Further readings
Textbooks such as Switching and Automata Theory, by Z. Kohavi, McGrawHill, New York, NY, 1978; Introduction to Switching Theory and Logical Design by F.J. Hill and G.R. Peterson, John Wiley & Sons, New York, NY, 1981; An Engineering Approach to Digital Design by W.I. Fletcher, PrenticeHall, Englewood Cli s, N.J., 1980; Logic Design Principles by E.J. McCluskey, PrenticeHall, Englewood Cli s, N.J., 1986; Introduction to Digital Logic Design by 8.12. Further readings 309 ARCHITECTURE structural OF seq_netw IS SIGNAL SIGNAL SIGNAL SIGNAL a1,a2,a3,a4,a5,a6: o11 : S0,R0,S1,R1 : Q0,Q0p,Q1,Q1p : BIT; BIT; BIT; BIT; BEGIN U1 : ENTITY and3 U2 : ENTITY and4 U3 : ENTITY and2 U4 : ENTITY and2 U5 : ENTITY and2 U6 : ENTITY and3 U7 : ENTITY and2 U8 : ENTITY or2 U9 : ENTITY and2 U10: ENTITY or2 U11: ENTITY or2 FF1: ENTITY SRff FF0: ENTITY SRff END structural; PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP (x0p,Q1,Q0,a1); (x1,x0,Q1,Q0p,a2); (x1p,Q0,a3) ; (x0p,Q1,a4) ; (x0p,Q1p,a5) ; (x1,x0,Q1,a6); (x1,Q1p,S1) ; (a1,a2,R1) ; (x1p,Q0p,S0) ; (a3,a4,R0) ; (a5,a6,z) ; (S1,R1,Q1,Q1p,clk); (S0,R0,Q0,Q0p,clk); Figure 8.36: Structural description for network in Figure 8.35. 310
Combinational network Chapter 8. Sequential networks Y Gated latches z y x CLK Figure 8.37: Network for Exercise 8.1. J.P. Hayes, AddisonWesley, Reading, MA, 1993; Digital Design Principles and Practices by J. F. Wakerly, 2nd Edition, Prentice Hall, Englewood Cli s, NJ, 1994; and Contemporary Logic Design by R. H. Katz, The Benjamin/Cummings Publishing Company, Redwood City, California, 1994, cover the analysis and synthesis of sequential networks at the binary level, specially using ip ops as the primitive component. For additional information on ip op characteristics, the reader can consult integrated circuits manuals such as the LSI Logic Databook and the Texas Instruments TTL Data Book for Design Engineers. 8.13 Exercises Timing in synchronous sequential networks Ex. 8.1 This problem is related to the limitations in the use of a gatedlatch, as discussed in Section 8.3. Consider the sequential network shown in Figure 8.37, which consists of gatedlatches and a combinational network. For a clock pulse width of 5 ns] and a latch propagation delay of 2 ns]: a) Determine the minimum delay of the combinational network in order to avoid races. b) If the delay of the combinational network can decrease by 30% from the minimum value computed in a) and the latch delay can decrease by 10%, determine the maximum clock pulse width that will guarantee no races. Ex. 8.2 For the canonical sequential network shown in Figure 8.38, determine the timing factors (in terms of the timing factors of cells and gates) for tin = 2:0 ns] and tout = 2:5 ns]. 8.13. Exercises 311
Y y 1 1 DQ FF1 Q’
x y 1 y
x z y
0 0 Y 1 0 DQ FF0 Q’ CLK z 0 t p = 0.5 ns for gates t su = 1.0ns for cells t p = 3.0ns for cells Figure 8.38: Network for Exercise 8.2. Combinational network Combinational network Gated latches Phase 1 Phase 2 Phase 1 Phase 2 Figure 8.39: Network for Exercise 8.3. Ex. 8.3 A generalization of the masterslave approach is depicted in Figure 8.39.
The network consists of two registers, formed by gatedlatches, and two combinational networks. The network has a twophase (nonoverlapping) clock, as shown in the gure, phase 1 being applied to one register and phase 2 to the other. a) Show that this con guration does not have race problems. b) How many states does the system have if each register has n cells? c) Implement the system of Exercise 8.4 using this con guration and compare the two implementations. Gated latches 312
x
1 0 Chapter 8. Sequential networks
Y y DQ FF1 Y x’
0 0 x’ x 1 1 0 y DQ FF0 0 z CLK Figure 8.40: Network for Exercise 8.4. diagram. Assuming that the initial state is 00, determine ve input patterns that the system recognizes (produces output 1). Analysis and design of canonical sequential networks Ex. 8.4 Analyze the pattern recognizer shown in Figure 8.40. Give a state Ex. 8.5 Obtain the canonical implementation of a pattern recognizer that recognizes the pattern 0101011. Ex. 8.6 Obtain the canonical implementation of a pattern generator that generates the continuous pattern abcaba. Ex. 8.7 Design a canonical sequential network whose output is 1 whenever the input sequence consists of a 1 followed by a block of 0's of even length, followed by two 1's, followed by a block of 0's of odd length. Ex. 8.8 Design a canonical sequential network that has the following state
table: PS A B C D E F Input x=0 x=1 B; a F; b C; a A; c D; a B; b E; b C; c F; b D; b A; c E; c NS; z Ex. 8.9 Design a canonical sequential network whose input is a sequence of decimal digits in BCD whose output is the minimum digit of the sequence. If some input does not correspond to a BCD digit the output should be 1111. 8.13. Exercises 313 Ex. 8.10 Implement a sequential (bitserial) network for converting an nbit representation of an integer from binary code to Gray code. Use the fact that gi = bi bi+1 , wherein bi is the ith bit of the binary representation and gi is the corresponding bit of the Gray code. Ex. 8.11 Implement a sequential (bitserial) binary adder/subtracter. A control input k indicates whether an addition (k = 1) or a subtraction (k = 0) is performed. Ex. 8.12 Implement a sequential (bitserial) binary magnitude comparator for 16 bit operands. Describe two implementations: one beginning with the most signi cant bit and the other with the least signi cant bit. Ex. 8.13 A combination lock opens when the string of decimal digits (0,5,6,8) is entered serially at its input. The lock has two binary outputs z1 and z2 . The correct combination produces z1 = 1 and an incorrect combination produces z2 = 1. The output has value 00 while the string is being entered. Implement this lock as a canonical sequential network.
diagram for the following sequence of JK inputs: 00, 10, 01, 11, 00. The initial state of the ip op is 0. Ex. 8.15 Design a gate network to implement a T ip op. Flip op modules Ex. 8.14 Design a gate network to implement a JK ip op. Show a timing state diagram. Analysis of networks with ip ops Ex. 8.16 Analyze the network shown in Figure 8.41. Give a state table and a Ex. 8.17 Analyze the network depicted in Figure 8.42. Give a timing diagram of its operation. Ex. 8.18 Analyze the network depicted in Figure 8.43. Give a state diagram and a highlevel description. Ex. 8.19 Analyze the network shown in Figure 8.44. Show that it produces a 1 at the output every six clock cycles. Ex. 8.20 Analyze the network given in Figure 8.45. Show that it is a modulo3 counter. Ex. 8.21 Analyze the network depicted in Figure 8.46. Show that it is a serial converter from BCD to Excess3. Give a timing diagram. 314 Chapter 8. Sequential networks Q B Q J Q A K Q’ A z z 3 Q x J Q B K Q’ B 2 z 1 z CLK 0 Figure 8.41: Network for Exercise 8.16. J x
CLK x Q
CLK J Q
CLK J Q z A K Q’ B K Q’ x’ C K Q’ Figure 8.42: Network for Exercise 8.17. T CLK Q A Q’ CLK T Q B Q’ z Figure 8.43: Network for Exercise 8.18. 8.13. Exercises 315 "1" J Q CLK
"1" J Q CLK
"1" J Q CLK
"1" A K Q’ B K Q’ C K Q’ z Figure 8.44: Network for Exercise 8.19. T CLK Q A Q’ CLK T Q B Q’ z Figure 8.45: Network for Exercise 8.20. x
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Q’ 1 Q S Q Q
1 2 Q 2 2 Q’ 0 FF2 Q’ R Q’ 2 Q J Q FF1 Q’ 1 K Q’ Q T Q
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2 Q 0 0 z Q Q
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0 Figure 8.46: Network for Exercise 8.21. 316 Chapter 8. Sequential networks op, a T ip op, and a JK ip op. Ex. 8.23 Design a sequential system with one binary input x and one binary output z . The output is 1 whenever two consecutive 1's followed by a 0 are observed, otherwise the output is 0. Use JK ip ops. Ex. 8.24 Design a sequential network that has one binary input x and one binary output z . The output at time t has value 1 whenever x(t 3; t) has an odd number of 1's. Overlapping sequences are acceptable; for example, for the input sequence x(t 7; t) = 01011111 the output sequence is z (t 7; t) =???01100 (the ? indicate that the output is not known because it depends on input values not given). Use D ip ops. Ex. 8.25 A sequential system has one binary input x and one binary output z . The output at time t has value 1 whenever x(t 1; t) = 11. Design a Mealy sequential network using JK ip ops. Ex. 8.26 Design a modulo3 binary counter using SR ip ops. Ex. 8.27 Design a cyclic counter with the output sequence 0,1,3,7,6,4,0,1... (of period 6) using JK ip ops. Compare the following two approaches in implementing the system: a) Select a state assignment that is the same as the coding for the output, that is z (t) = s(t). b) Select the state assignment for a modulo6 binary counter and implement the required output function. Ex. 8.28 An up/down counter counts up or down depending on the value of a binary control signal. Design a modulo7 binary up/down counter using: a) Three T ip ops. b) Three D ip ops. c) Two T ip ops (for the two leastsigni cant ip ops) and one D ip op. Ex. 8.29 Design a sequential system with one binary input x and one binary output z . The output at time t is 1 whenever x(t 3; t) = 0101 or 0110. Implement using JK ip ops and nand gates. Design of networks with ip ops Ex. 8.22 Using a D ip op, design networks that correspond to an SR ip 8.13. Exercises 317 and compare the two implementations with respect to the number of gates required. Ex. 8.30 Design the sequential system given in Example 8.8 using D ip ops Ex. 8.31 Design the sequential system given in Example 8.9 using JK ipops and compare the two implementations with respect to the number of gates required. Ex. 8.32 Design a modulo3 binary counter using the \one ip opperstate" approach. The output is in the binary code. Ex. 8.33 Design a sequential network described by the following state/output
table PS A B C D E F using the \onehot" approach. Input x=0 x=1 B; a F; b C; a A; c D; a B; b E; b C; c F; b D; b A; c E; c NS; z Ex. 8.34 Design a sequential network with a shifting state register. The network has one binary input x and one binary output z . The output is 1 whenever three consecutive 1's are followed by two 0's, otherwise the output is 0. Descriptions in
vhdl All the exercises corresponding to analysis and design can be done using vhdl. ...
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This note was uploaded on 03/26/2010 for the course CS 187154200 taught by Professor Ercegovac,m.d. during the Winter '09 term at UCLA.
 Winter '09
 Ercegovac,M.D.

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