Unformatted text preview: Chapter 8 Sequential networks
In this chapter we discuss: Canonical form of sequential networks: state register plus combinational network. Characteristics of binary cells: latches and edgetriggered cells. The D ip op. Timing parameters for cells and networks: setup time, hold time, and propagation delay. Example for a family of cmos modules. Analysis and design of canonical networks. Other ip op modules: SR, JK and T ip op. Tables, state diagrams and characteristic equations. Analysis of ip op networks. Design of ip op networks. The excitation functions. Special state assignments: one ip opperstate and shifting register. Speci cation of sequential networks in vhdl. In the same way as for combinational systems (see Chapter 4), the realization of a sequential system involves a circuit level and a logic level. The circuit level deals with the physical realization of elementary sequential modules. In contrast, the logic level consists of the realization of a sequential system by a collection of simpler networks, both combinational and sequential, leading to a sequential network. As in the case of combinational systems, the network concept can be used at several levels in a hierarchical manner (a module in a network can itself be realized as a network of simpler modules). We begin studying the realization of synchronous sequential systems by showing a canonical implementation, which consists of a set of binary cells 257 258 Chapter 8. Sequential networks to store the state and combinational networks to realize the output and transition functions. Consequently, the only additional element required for the implementation is the binary cell. We show how this cell, called the D ipop, can be realized by a gate network in which the sequential operation is achieved by a loop in the network. A standard form for all sequential networks is the canonical implementation (also called Hu manMoore implementation), which is based directly on the state description of a system: Statetransition function s(t + 1) = G(s(t); x(t)) Output function z (t) = H (s(t); x(t)) This implementation, whose components are organized as depicted in Figure 8.1a, consists of a state register to store the state; and a combinational network to implement the transition and output functions. Since the system is synchronous, a synchronizing signal (called the clock CLK) determines the time instants at which the next state is loaded into the state register. At time t, the next state is loaded into the state register and remains stored there until time t + 1. The clock consists of periodic clock pulses (see Figure 8.1b), which in the ideal case have zero width. Actual clock pulses, whose nonzero width a ects the operation of the sequential network, are discussed in Section 8.3. In general, the description of a sequential system includes an initial state, being necessary to bring the system into such a state in order to have the desired inputoutput behavior. This initialization is accomplished by a special input initialize. For simplicity, in this book we usually do not indicate the initialization signal but assume that it is implemented as required. From the discussion in Section 7.1.3, any sequential system is classi ed either as a Mealy or Moore machine. The canonical form of these systems di er slightly, as illustrated in Figure 8.2. In a Mealy machine, the networks for both the transition function and the output function have the external input x(t) and the state s(t) as inputs, whereas in a Moore machine the network implementingthe output function has only s(t) as input. It should be noted that the separation of the combinational network into two independent subnetworks is made only to illustrate the di erence; in a practical implementation, this separation would not necessarily be made because both networks could share some modules. 8.1 Canonical form of sequential networks 8.1. Canonical form of sequential networks 259 State Register Combinational Network next state
s(t+1) initialize present input
x(t) s(t) present state CLK z(t) (a) present output Ideal clock pulse PRESENT STATE s(t) t NEXT STATE s(t+1) Ideal clock t
0 1 2 3 4 5 (b) 6 7 Figure 8.1: a) Canonical implementation of sequential network. b) Ideal clock signal and its interpretation. 260 Chapter 8. Sequential networks s(t+1) C1 x(t) State Register s(t) C2 z(t) CLK (a) State Register s(t+1) C1 x(t) z(t) C2 s(t) CLK (b) Figure 8.2: Canonical implementations: a) Mealy machine. b) Moore machine. 8.2. Highlevel and binary implementations
Initialize z0 Y0 Y1 Y k1 y y y Outputs z n1
0 1 261 Inputs x m1 x0 Combinational Network State Register (binary cells)
k1 Next state Present state CLK Figure 8.3: Canonical implementation with binary variables. 8.2 Highlevel and binary implementations
The highlevel description of the canonical form of a sequential system uses multivalued variables for input, state and output. This compact and manageable description is used whenever the particular binary representation is not signi cant. On the other hand, as we have discussed for combinational networks, the physical implementation of digital systems uses binary variables. Consequently, a highlevel description must be converted into a binary description by introducing codes for the input, output, and state variables, so that the variables x, s, and z are represented by the bitvectors x, s, and z , respectively. The canonical form of a binary system is illustrated in Figure 8.3. In this implementation, the state register consists of k binary cells, wherein k is the number of state variables. Each binary cell has a binary input (the next state), a binary output (the present state), and a synchronizing input (the clock). As depicted in the gure, it is customary to denote the presentstate vector (PS ) by y and the nextstate vector (NS ) by Y . Example 8.1 Figure 8.4 depicts the (binary) canonical form of a sequential
system having the following description: 262
x0 x1 Initialize Combinational Network Y0 Y1 Y2 Y3 y
0 Chapter 8. Sequential networks y 1 y 2 y
3 z CLK Figure 8.4: Canonical network for Example 8.1. Input: Output: State: Initial state: Function: x(t) = (x1 ; x0); xi 2 f0; 1g z (t) 2 f0; 1g y (t) = (y3 ; y2 ; y1; y0 ); yi (t) 2 f0; 1g y (0) = (0; 0; 0; 0) The transition and output functions are Y3 Y2 Y1 Y0 = = = = y2 x01x0 (y1 y2 )x00 y3 x1 (y0 y3 )x01 x0 (y0 y1 )x1 (y0 y3 )x00 y1 x01x0 y2 x1 z = y3 y2 y1 y0 8.3 Gatedlatch and D ip op
So far we have considered the ideal case in which the clock pulse has zero width, and the binary cells change state instantaneously. In practice, the clock pulse has a nite width and the cell has some timing characteristics that have to be taken into account for a satisfactory operation of a system. These characteristics also determine the speed of the resulting network. The basic characteristics of the clock signal with respect to network timing, depicted in Figure 8.5, are the clock period T (or the clock frequency f = 1=T ); and 8.3. Gatedlatch and D ip op
CLK t
w 263 Clock pulse width Clock period T time Figure 8.5: Pulse width and clock period. the (clock) pulse width tw . Let us now consider the characteristics required from binary cells so that they perform adequately in a synchronous sequential network. The most basic binary cell is called a (controlled) gatedlatch; it has one binary input signal D (for data), one binary output signal Q, and an enable input E , as shown in Figure 8.6a. The output of the cell corresponds to the state; this output follows the value of the input when E = 1 and does not change (is latched) when E = 0, so the cell is called levelsensitive (in contrast to the edgesensitive cell discussed later) The change of value of the output signal has a propagation delay tp with respect to a change in the enable signal (see Figure 8.6b). That is, Q(t + tp ) = D(t) E (t) Q(t) E 0 (t) Figures 8.7 and 8.8 show two alternative implementations of a gatedlatch. These implementations consist of a gate network which includes a loop that is responsible for storing the state. In the rst implementation, the loop consists of two nor gates. The operation, illustrated by the timing diagram in Figure 8.7b (wherein the arrows indicate \causee ect" relations among signal changes), is as follows: When E = 1, signals b and d correspond to the value of D and D0 , respectively. Two situations can occur: if b = 1 and d = 0, then c = 0 and Q = 1; and if b = 0 and d = 1, then Q = 0 and c = 1. Consequently, in both cases Q = D. When E = 0, b = d = 0 and the loop is used to latch the value of Q. In the second implementation (see Figure 8.8), the operation is as follows: When E = 1, the upper transmission gate corresponds to a closed switch and the lower transmission gate corresponds to an open switch. Therefore, the value of the output Q is equal to the input D. 264 Chapter 8. Sequential networks D Q E (a) E D Q t p t p (b) Figure 8.6: a) Gatedlatch. b) Timing behavior. 8.3. Gatedlatch and D ip op 265 D (Input) b c E (Enable) a d Q (Output) (a) E D a b c d Q * c kept in 0 even when b=0 + Q kept in 0 even when d=0 (b) loop * + loop Figure 8.7: a) Implementation of gatedlatch with nor gates. b) Timing diagram. 266
TG1 D (Input) E (Enable) c b d a TG2 Chapter 8. Sequential networks Q (Output) e f (a) E a b TG1 TG2 D c d f Q loop loop on on off off (b) diagram. Figure 8.8: a) Implementation of gatedlatch with transmission gates. b) Timing When E = 0, the situation reverses so that the input is disconnected from the output and the twoinverter loop maintains the state. In both implementations, the (noninverting) loop is the basis for the operation of the network as a sequential system.1 In the second implementation, the inverters in the loop are needed to compensate for the voltage drop across the transmission gate. Limitations of gatedlatch for use in a synchronous network
The gatedlatch could be used in a synchronous sequential system by connecting the clock to input E , but this might not produce the desired behavior. To show
1 An inverting loop produces an oscillator, in which the output changes periodically from 0 to 1 to 0, the period depending on the delay in the loop. 8.3. Gatedlatch and D ip op 267 this, consider the sequential system with state description s(t + 1) = s(t) x(t) whose implementation is depicted in Figure 8.9a. If the clock pulse is narrow (smaller than the delay of the gatedlatch), the system operates correctly as indicated in the timing diagram depicted in Figure 8.9b. The state changes at most once per clock pulse, and the system behavior corresponds to the statetransition function described above. On the other hand, if the width of the clock pulse is larger than the gatedlatch delay, then the operation is as indicated in Figure 8.9c. The new value of the state is fed back to the gatedlatch input while the clock signal is still 1, which produces another change of state. The behavior of the system does not correspond to the expected statetransition function. If the clock pulse is even wider, then more than two state changes could occur. This behavior of multiple state changes per clock pulse is called a race condition, and must be avoided for correct operation. Example 8.2 If the minimumpropagation delay of the xor gate in Figure 8.9a is 1.5 ns] and the minimum propagation delay of the latch is 1.2 ns], then the maximum width of the clock pulse to avoid races is 2.7 ns]. Consequently, the correct behavior of a synchronous sequential network depends on the relative values of the pulse width and the gatedlatch delay. The desired values of these parameters con ict: small gatedlatch delays are desirable for fast network operation, but very narrow clock pulses are not easily realizable. Moreover, the gatedlatch delay and the clock width might have variations during the operation of the system. Thus, a gatedlatch as the binary cell of a synchronous sequential system does not lead to reliable operation, so that other type of cells must be used. The solution to the above mentioned problem consists in using an edgetriggered cell (also called edgesensitive cell, in contrast to the levelsensitive cell considered before). In this new cell, loading of a new state is caused (triggered) by the transition (edge) of the clock signal instead of by its value (level). Edgetriggered cell As shown in Figure 8.10, two types of edgetriggered cells exist, depending on which edge produces the state change: Leadingedgetriggered cell (also called positiveedge triggered). The triggering transition is the rst (rising) edge of the pulse, when the clock changes from 0 to 1. Trailingedgetriggered cell (also called negativeedge triggered). The transition occurs at the second (falling) edge, when the clock changes from 1 to 0. 268 Chapter 8. Sequential networks CLK x t y
p x Y D y Q CLK E z Y t XOR t XOR (b) CLK (a) x t y
p t p Y t XOR t t
XOR XOR (c) Figure 8.9: a) Sequential network. b) Correct timing behavior. c) Incorrect timing
behavior. 8.3. Gatedlatch and D ip op
Input D Output Q CLK (a) Triggering edge CLK CLK CLK (b) Triggering edge Q Input D Output 269 x tp y x tp y Y Y (c) (d) Figure 8.10: Edgetriggered cell: a) Leadingedgetriggered cell. b) Trailingedge triggered cell. c) Leadingedgetriggered cell in network of Figure 8.9. d) Trailingedgetriggered cell in network of Figure 8.9. Since there is only one edge of each type per clock pulse, this type of operation assures that at most one change of state occurs per clock cycle. Figure 8.10 illustrates the convention used for designating both types of edgetriggered cells, and the timing diagram for the network depicted in Figure 8.9 when an edgetriggered cell is used. Masterslave implementation Edgetriggered cells can be implemented with a masterslave structure, which consists of two gatedlatches as shown in Figure 8.11a.2 The clock signal is connected to input E of the rst latch (called the master) so that its output follows the input to the cell while the clock signal has value 1, and does not change when the clock has value 0. In contrast, the complement of the clock is connected to input E of the second latch (called the slave) so that its output 2 Some TTLoriented texts make a distinction among a masterslave cell and an edgetriggered cell. However, since the behavior is the same and the masterslave implementation is used in cmos, we do not make such a distinction. 270 Chapter 8. Sequential networks follows its input (which corresponds to the output of the master cell) while the clock has value 0, and does not change when the clock has value 1. As shown in Figure 8.11b, the input to the masterslave cell is loaded into the master cell during the clock pulse, and is transferred to the slave cell after the clock pulse has terminated. This assures that the change of state (output S ) occurs when the clock changes from 1 to 0, so the cell is trailingedge triggered. As a followon to the discussion above, a leadingedgetriggered cell is obtained by connecting the complemented clock signal to the master cell and the uncomplemented clock signal to the slave cell. The edgetriggered binary cell just presented is called a D ip op. As shown in Figure 8.12, the D ip op has one input called D (data) and two outputs corresponding to the state (Q) and its complement (Q0 ). The complement output is optional. When Q = 1 the ip op is said to be in the \one" or \set" state; similarly, when Q = 0 it is in the \zero" or \reset" state. An additional input, called CLK, receives the clock signal. The transition function of a D ip op is PS = Q(t) D(t) 0 1 0 0 1 1 0 1 NS = Q(t + 1) That is, the next state Q(t + 1) corresponds to the value of the input D(t). Thus, the D ip op is called a \delay" ip op. Equivalently, the operation can be described by the characteristic expression: Q(t + 1) = D(t) or by the state diagram shown in Figure 8.12. Note that the binary cells of the state register in the canonical implementation (see Figure 8.4) precisely correspond to D ip ops. A D ip op may also have \asynchronous" inputs, usually labeled PR (preset) and CLR (clear), which are used to force the ip op into the 1 or 0 state, respectively, independent of other inputs and the clock. Preset and clear are used to initialize ip ops at the beginning of the system operation. Since we are concerned with synchronous sequential systems, we will not include preset and clear inputs in logic diagrams and textual speci cations. We now discuss some basic timing parameters of binary cells. More speci cally, we consider a leadingedge triggered cell in which the change of state is caused D ip op Timing parameters of a binary cell 8.3. Gatedlatch and D ip op 271
W S Input I D Q D Q Output CLK E Master cell E Slave cell CLK’ (a) CLK I W CLK’ S t
p t p W latched (b) S latched Figure 8.11: a) Masterslave implementation of trailingedgetriggered cell. b)
Masterslave state change process. PR (preset) INPUT D(t) CLK 1 OUTPUTS 0 Q=0 0 Q=1 1 DQ Q’ Q(t) Q’(t) (optional) CLR (clear) Figure 8.12: D ip op and its state diagram. 272
CLK setup time
Input
D Q CLK Chapter 8. Sequential networks
tw t su th hold time State Input State tp propagation delay Figure 8.13: Time behavior of cell. by the leading edge of the clock pulse. With respect to this synchronizing event, the following timing parameters are de ned (see Figure 8.13): Setup time (tsu) is the minimum time interval from the stabilization of the
cell input to the triggering edge of the clock. Hold time (th ) is the minimum time interval from the triggering edge of the
clock to a subsequent change in the input to the cell. Pulse width (tw ) is the minimum width of the synchronizing clock pulse. Propagation delay (tp) is the time interval from the triggering edge of the clock to the stabilization of the new state (cell output). When appropriate, we distinguish lowtohigh (tpLH ) and hightolow (tpHL ) propagation delays. As for gates, the propagation delay depends on the load connected to the cell output. The characteristics of a cmos D ip op (of the same family as the gates of Chapter 3) are shown in Table 8.1. In addition to the timing characteristics, the load factor and the size of the module are given; these are de ned in the same manner as for gates. 8.4 Timing characteristics of sequential networks
We now determine the timing parameters of a sequential network in the canonical implementation, in terms of the timing parameters of the binary cells and 8.4. Timing characteristics of sequential networks 273 Table 8.1: Characteristics of a cmos D ip op Input Size factor tpLH tpHL tsu th tw std. equiv. ns] ns] ns] ns] ns] loads] gates] 0:49 + 0:038L 0:54 + 0:019L 0:30 0:14 0.2 1 6 L: output load of the ip op This ip op has only the uncomplemented output the delays of the associated combinational networks. For simplicity, we consider a Mooretype sequential network; the extension to a Mealytype network is straightforward. Figure 8.14 depicts a canonical network in which d1x and d1y are the delays of combinational network C 1 with respect to input x and to the feedback input from the state register y, respectively. Moreover, d2 is the delay of the output network C 2. Then, the following relationships hold: Network setup time. As illustrated in Figure 8.14b, the cell setup time restriction requires that the input to the cell be stable at t . Since the cell input corresponds to the output from network C 1, which has a delay d1x, the input x to the network must be stable that much earlier. That is, tx (net) = d1x + tsu(cell) su Delays Network hold time. Since the network input x changes a time interval d1x before the cell input Y , it would seem that the network hold time should be th (cell) d1x. However, d1x is the maximum delay between the stabilization of x and that of Y , but Y might begin to change earli...
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 Winter '09
 Ercegovac,M.D.
 Clock signal, Clock distribution network, Sequential Networks, Combinational Networks

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