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CSM51Ach9 - 318 Chapter 9 Standard combinational modules In...

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Unformatted text preview: 318 Chapter 9 Standard combinational modules In this chapter, we present A set of widely used standard combinational modules. The speci cation of these standard modules. A gate network implementation for each of these standard modules. The main uses of these standard modules. The implementation of large modules as networks of smaller ones. Complex digital systems are implemented as modular networks. Although fully custom-designed modules are used in special cases, most frequently the systems are built using standard modules. These standard modules correspond to subfunctions that have been identi ed as useful for a large variety of applications, and have been made available as \o -the-shelf" and library components, that is, ready to use as part of a modular network. This approach is applicable at all levels of integration (msi, lsi, vlsi). The design of a system using standard modules consists of two steps: decompose the overall functionality of the system into subfunctions that can be mapped onto standard components; and interconnect the chosen standard components as a modular network. If the decomposition still produces complex subfunctions, a new level of decomposition is applied until the mapping of subfunctions onto standard components becomes feasible. 319 320 Chapter 9. Standard combinational modules E En y 0 0 1 2 n-Input Binary Decoder y 1 2 x y x 1 1 x n-1 n-1 n 2 -1 yn 2 -1 Figure 9.1: n-input binary decoder. In this chapter, we begin the study of standard modules by introducing a set of widely used combinational components, namely decoders, encoders, multiplexers, demultiplexers and shifters. We de ne the function of these modules, give high-level and binary-level descriptions, and indicate their basic use. We also describe how to construct networks of these standard modules. Other standard combinational and sequential modules are described in the following chapters. 9.1 Binary decoders An n-input binary decoder (see Figure 9.1) is a combinational system that has n binary inputs x = (xn 1; : : :; x0) and 2n binary outputs y = (y2n 1; : : :; y0). The input vector x can be considered as representing integers from 0 to 2n 1 in the radix-2 representation. At any given time, at most one binary output { say yi { is equal to 1 and all other outputs are equal to 0; yi = 1 indicates that the input bit-vector represents the integer i. That is, the module can be regarded as a code converter from the binary code to the 1-out-of-2n code. An additional input, called module enable E , is used to facilitate the implementation of network of decoders; when E = 0, all outputs from the module are equal to 0 (or they are in the high-impedance state for three-state outputs). A high-level description of an n-input binary decoder is Outputs 0 0 Inputs 9.1. Binary decoders 321 x = (xn 1; : : :; x0); xj 2 f0; 1g E 2 f0; 1g y = (y2n 1 ; : : :; y0 ); yi 2 f0; 1g 1 if (x = i) and (E = 1) 0 otherwise P Inputs: Outputs: Function: yi = n wherein x = j =01 xj 2j and i = 0; : : :; 2n 1 Example 9.1 The function of a 3-input binary decoder is described by the following table: E x2 x1 x0 x y7 y6 y5 y4 y3 y2 y1 y0 1000000000001 1001100000010 1010200000100 1011300001000 1100400010000 1101500100000 1110601000000 1111710000000 0----00000000 Each decoder output corresponds to a switching function having value 1 for exactly one assignment, so it can be represented by one minterm. Consequently, the binary speci cation is given by Inputs: x = (xn 1; : : :; x0); xj 2 f0; 1g E 2 f0; 1g Outputs: y = (y2n 1; : : :; y0); yi 2 f0; 1g Function: yi = E mi (x) ; i = 0; : : :; 2n 1 wherein mi (x) is the i-th minterm of the n variables x A gate network implementation consists of n not gates and 2n and gates with n + 1 inputs each. Example 9.2 The switching expressions describing a 2-input binary decoder are y0 = x01x00E y1 = x01x0E y2 = x1x00E y3 = x1x0E 322 Chapter 9. Standard combinational modules E y x 0 0 1 2 y x y y 1 3 Figure 9.2: Gate network implementation of a 2-input binary decoder. A gate network implementation of this binary decoder is shown in Figure 9.2. As a short-hand notation, a decoder module is denoted by y = dec(x; E ) For example, for a three-input decoder, y = dec((1; 1; 0); 1) = (0; 1; 0; 0; 0; 0; 0; 0) Uses A binary decoder is used whenever a set of values has been encoded using a binary code and they have to be separated, that is, decoded. Speci cally, a set of 2n elements can be encoded on n binary variables. Then, an n-bit decoder can be used to identify which element of the set has been encoded. Typical examples are decoding the operation code (opcode) in a computer instruction, or decoding the address (location) referenced when accessing a memory. up to 16 di erent operations can be speci ed. Part of the instruction execution process consists of determining the operation speci ed in the instruction. A binary decoder can be used for these purposes, as shown in Figure 9.3. Example 9.3 A computer instruction has an opcode eld of four bits, so that Figure 9.4), a 1-bit data input, a 1-bit data output, and one control input to 1 The notation 1K is used to denote 1024=2 Example 9.4 A 16K 1 memory module stores 16K1 words of 1 bit each. This module has a 14-bit address used to specify one particular word input (see 10 , so that 16K denotes 16384=2 14 . 9.1. Binary decoders OPCODE field Instruction Other fields 323 E=1 En 4-Input Binary Decoder 15 . . . 4 3 2 1 0 LOAD STORE ADD JUMP Decoded operations Figure 9.3: Operation decoding. specify a memory operation (read or write). The implementation of the module consists basically of two parts: an array of 16K binary cells, each storing one bit, and a binary decoder that selects one of the cells for a read or write operation. Due to its size, this decoder cannot be implemented with a gate network of the type shown in Figure 9.2; a network of decoders has to be used instead, as discussed later. Decoders also exist for other input representations. For example, decimal decoders have ten outputs for codes such as BCD and Excess-3; their de nition and implementation are similar to those of the binary decoder, so we do not discuss them further. An n-input binary decoder and an or gate can realize any switching function of n variables, so that these two components correspond to a universal set of combinational modules. This is a consequence of the de nition of a binary decoder: since the i-th decoder output corresponds to minterm mi (x), then the implementation of any sum of minterms is obtained by performing an or with the outputs of the decoder that correspond to the minterms in the expression. Moreover, several functions of the same variables can be generated with one decoder and with one or gate per function. 9.1.1 Binary decoder and or gate as universal set Example 9.5 Consider the combinational system described by the following table: 324 Chapter 9. Standard combinational modules Cell referenced when address is Data input 00000000000010 Data input Binary cell E=1 Address 14 RAM Module (2 14 x 1) Address 14 Binary Decoder 0 1 2 16383 Read/write Read/write Data output (a) (b) Data output cells. Figure 9.4: Random-access memory (RAM): a) module; b) addressing of binary x2 x1x0 z2 z1 z0 000 010 100 001 010 001 011 010 100 001 101 101 110 000 111 100 This system can be implemented using a three-input binary decoder and or gates, as shown in Figure 9.5 and described at the binary level as follows: (y7 ; : : :; y0) = dec(x2 ; x1; x0; 1) z2 (x2 ; x1; x0) = y1 y5 y7 z1 (x2 ; x1; x0) = y0 y3 z0 (x2 ; x1; x0) = y2 y4 y5 9.1.2 Decoder networks 9.1. Binary decoders E=1 En 325 0 1 y0 y1 Binary Decoder y 2 3 2 z2 x0 x 1 0 1 2 y3 y4 4 5 z1 x2 y5 y 6 z0 6 7 y7 Figure 9.5: Network in Example 9.5. Due to limitations in the maximum number of connections to a module and the number of gates in an implementation, standard modules implement decoders with a small number of inputs (i.e., four inputs). Larger decoders are often required but it is impractical to implement them as one module, so that decoders networks are used instead. We now discuss two approaches for the design of these networks: coincident decoding and tree decoding. Let us consider the implementation of an 8-input binary decoder using standard 4-input binary decoders. For these purposes, let us divide the 8-bit input vector (x7; x6; :::; x1; x0) into two four-bit subvectors, as follows: x = (xleft ; xright ) xleft = (x7 ; x6; x5; x4) xright = (x3 ; x2; x1; x0) The coincident decoder is built as illustrated in Figure 9.6, wherein each subvector is decoded by one 4-input decoder, producing the vectors y = (y15 ; : : :; y0 ) and w = (w15; : : :; w0). Then, every pair consisting of one output from each decoder is applied as input to one of 256 2-input and gates. The outputs from these gates correspond to the outputs from the 8-input decoder. Outputs are labeled by noting that x = 24 xleft + xright where x, xleft , and xright are the integers represented by x, xleft , and xright , respectively. Consequently, zi corresponds to the output from the and gate Coincident decoding 326 x7 x6 Chapter 9. Standard combinational modules x5 x4 x3 x2 x1 x0 0 E En 0 1 0 1 0 En 1 0 0 4-Input Binary Decoder ... 210 4-Input Binary Decoder . . .4 3 2 1 0 15 15 y 2 w 4 1 1 0 z 255 1 z 36 0 z0 Figure 9.6: 8-input coincident decoder. with inputs ys and wt , wherein i = 24 s + t For example, output z36 is obtained from the and gate whose inputs are y2 and w4 because 36 = 24 2 + 4. The external (network) enable input E is connected to the enable input to one decoder module, whereas the enable input to the other module is set to 1. Consequently, if E = 0 then all outputs from one decoder module are 0, resulting in zi = 0 for all i. As a generalization of this network, an n-input binary decoder is implemented by two (n=2)-input binary decoders and 2n and gates, as indicated in Figure 9.7. The input to decoder W is xright = (x n 1 ; : : :; x0), whereas the 2 input to decoder Y is xleft = (xn 1; : : :; x n ). The network enable input is 2 connected to the enable of one of the decoders (for example Y ). A functional description that captures the network shown in Figure 9.7 is y = dec(xleft ; E ) w = dec(xright ; 1) z = (and(y2n=2 1; w2n=2 1); : : :; and(ys ; wt); : : :; and(y0 ; w0)) Tree decoding 9.1. Binary decoders 327 x n/2-1 x0 1 En DECODER W w n/2 2 -1 wt w0 z0 y0 x n/2 x n-1 DECODER Y ys En y n/2 2 -1 E z n/2 2 s+t zn 2 -1 Figure 9.7: n-input coincident decoder. 328 Chapter 9. Standard combinational modules Another approach to the implementation of large decoders is a tree-decoder network. For this case, let us consider the implementation of a 4-input binary decoder using standard 2-input binary decoders. As in the coincident decoder, let us divide the 4-bit input vector into two 2-bit subvectors, as follows: x = (xleft ; xright ) xleft = (x3 ; x2) xright = (x1 ; x0) Based on this decomposition, we can build a two-level tree network which has one decoder in the rst level and four decoders in the second level, as depicted in Figure 9.8. xleft is decoded in the rst level whereas xright is decoded in the second level. The 16 network outputs are partitioned into four groups of four outputs each, where each group is produced by one decoder module. The operation is as follows: each output from decoding xleft enables one of the decoders in the second level; and the decoding of xright produces the corresponding output from the enabled decoder. For example, if x = (0; 1; 1; 0) then xleft = (0; 1) so that decoder DEC1 is enabled. Moreover, xright = (1; 0), which produces a 1 at output 2 of decoder DEC1, that is, at output 4 1 + 2 = 6. Note the essential role of the decoder enable input in the operation of this network. In general, an n-input decoder can be implemented by a two-level tree with one ( n )-input decoder in the rst level and 2n=2 ( n )-input decoders in the 2 2 second level, as depicted in Figure 9.9. A functional description that captures the network shown in Figure 9.9 is w = dec(xleft ; E ) z = (dec(xright ; w2n=2 1); : : :; dec(xright ; wt); : : :; dec(xright ; w0)) The tree-decoder network can be generalized to a multilevel tree. If n = rk, wherein k is the number of inputs to a decoder module, then k input variables are introduced at each level producing a tree of r levels. The number of decoder modules in such a case is 1 + 2k + 22k + : : : + 2(r 1)k = (2n 1)=(2k 1) For example, for n = 12 and k = 4, there are r = 3 levels and the number of modules is (212 1)=(24 1) = 273. 9.1. Binary decoders x3 x=6: 0 1 329 x2 1 0 DEC 2 1 0 x1 1 0 x0 Level 1 E En 3 0 0 1 0 1 0 DEC 3 En 1 0 DEC 2 En 1 0 DEC 1 En 1 0 DEC 0 En Level 2 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 0 z 15 0 0 0 z 12 0 0 0 0 z8 0 1 z 6 =1 0 0 z4 0 0 0 0 z0 Figure 9.8: 4-input tree decoder. The following table compares the two decoder networks just presented. Each network implements a 2k-input decoder using k-input decoder modules and 2-input and gates. Coincident Tree Decoder modules 2 2k + 1 2k and gates 2 { Load per network input 1 decoder input 2k decoder inputs (max) Fanout per decoder output 2k and inputs 1 enable input Number of module inputs 2k + 2 + 22k+1 1 + k + 2k + k2k (related to number of connections) Delay tdecoder + tAND 2tdecoder Example 9.6 A six-input decoder is implemented using coincident- and treedecoder networks, as illustrated in Figure 9.10. As shown in the following table, the coincident scheme requires two 3-input decoders and 64 two-input and gates. If the delay of decoders and and gates are 2d and d, respectively, then the total delay is 3d. On the other hand, the tree decoder requires nine decoder modules and its delay is equal to 4d. Comparison of decoder networks 330 Chapter 9. Standard combinational modules x x n-1 x left x n/2 right x0 x n/2-1 Level 1 E En DEC w n/2 2 -1 wt w0 En En DEC t DEC 0 En Level 2 n/2 DEC 2 -1 zn 2 -1 z 2 (n/2)t+s z0 Figure 9.9: n-input two-level tree decoder. E Decoder x0 x1 x2 0 1 7 z0 z1 E x1 x2 0 1 7 Decoder x0 0 1 7 z0 z1 z7 1 x4 x5 0 1 7 (a) z 63 Decoder x3 x4 x5 Decoder x3 Decoder 0 1 7 z 56 z 57 z 63 (b) decoder. Figure 9.10: Implementation of 6-input decoder. a) Coincident decoder. b) Tree 9.2. Binary encoders 331 Coincident 2 64 1 decoder input 8 and inputs 136 3d Tree 9 { 8 decoder inputs (max) 1 enable input 36 4d Decoder modules and gates Load per network input Fanout per decoder output Number of module inputs Delay As it can be inferred from the example above, the tree-decoder network is better than the coincident network in terms of the number of interconnections. Coincident-decoding, on the other hand, allows a reduction in the complexity of the connections from the generation of the decoding function to its use in other parts of the network. This is illustrated by the implementation of the system shown in Figures 9.11a and 9.11b, which consists of a 12-input decoder and an array of 4096 storage cells; each cell is selected by one output from the decoder. In the case of the tree network, 4096 lines go from the decoder to the array as depicted in Figure 9.11a. On the other hand, in the case of the coincident network, the and gates can be part of the array of cells so that just 128 lines are required (see Figure 9.11b). 9.2 Binary encoders A 2n-input binary encoder (see Figure 9.12) is a combinational system that has 2n binary inputs x = (x2n 1 ; : : :; x0) and n binary outputs y = (yn 1 ; : : :; y0 ). This module performs the inverse function of a decoder: it converts from the 1-out-of-2n code into a binary code. At any given time, at most one of the inputs { say xi { may be equal to 1 and all other inputs must be equal to 0; the output bit-vector represents, in a binary code, the index of the input with the value 1 (that is, i). An additional input and an additional output, called module enable E and module active A, respectively, are used to facilitate the implementation of encoders networks. The enable input has the same functionality as in the case of decoders, whereas output A indicates whether the module is \active" (that is, there is an input with value 1). A high-level description of a binary encoder is 332 Decoder Chapter 9. Standard combinational modules Cell array Binary cell E=1 0 1 2 0 1 2 Data input 12 Address Tree Decoder 4095 4096 lines from decoder to cell array Read/write 4095 Data output (a) Decoder E=1 Cell array 0 0 Data input 6 Binary Decoder 63 1 12 Address E=1 6 Binary Decoder 0 63 4095 Read/write 128 lines from decoder to cell array equivalent to coincident decoder (b) Modified binary cell Data output Figure 9.11: a) System with tree decoder. b) System with coincident decoder. 9.2. Binary encoders E En 333 x x 0 1 0 1 -Input Binary Encoder y 0 1 0 1 y n-1 n-1 xn 2 -1 n 2 -1 Ac A Figure 9.12: 2n -input binary encoder. Inputs: x = (x2n 1 ; : : :; x0); xi 2 f0; 1g, with at most one xi = 1 E 2 f0; 1g Outputs: y = (yn 1; : : :; y0); yj 2 f0; 1g A 2 f0; 1g i 0 1 A= 0 Function: y = if (xi = 1) and (E = 1) otherwise if (some xi = 1) and (E = 1) otherwise Pn 1 y j =0 j wherein y = 2j and i = 0; : : :; 2n 1 Example 9.7 The function of an 8-input binary encoder is given by the following table: 2 n Outputs Inputs y 334 Chapter 9. Standard combinational modules E x7 x6 x5 x4 x3 x2 x1 x0 y 1000000010 1000000101 1000001002 1000010003 1000100004 1001000005 1010000006 1100000007 1000000000 0--------0 y2 y1 y0 000 001 010 011 100 101 110 111 000 000 A 1 1 1 1 1 1 1 1 0 0 Notice that if xi = 1, then yj is 1 if the binary representation of i has a 1 in its j -th bit. Consequently, the binary speci cation of a n-bit encoder is: Inputs: x = (x2n 1 ; : : :; x0); xi 2 f0; 1g, with at most one xi = 1 E 2 f0; 1g Outputs: y = (yn 1; : : :; y0); yj 2 f0; 1g A 2 f0; 1g P P (xk ); Function: yj = E A=E j = 0; : : :; n 1 (xi); i = 0; : : :; n 1 wherein xk is included in the expression for yj if the j -th bit of the binary representation of k is 1. Example 9.8 The switching expressions describing a 8-input binary encoder are y0 y1 y2 A = = = = E E E E (x1 (x2 (x4 (x0 x3 x3 x5 x1 x5 x6 x6 x2 x7 ) x7 ) x7 ) x3 x4 x5 x6 x7 ) A gate-network implementation of this binary encoder is given in Figure 9.13. Uses A binary encoder is used whenever the occurrence of one of several disjoint events needs to be represented by an integer identifying the event. 9.3. Priority encoders x7 x6 x5 x4 x3 x2 x1 x0 335 E y0 y1 y2 A Figure 9.13: Implementation of an 8-input binary encoder. Example 9.9 A device determines the direction of the wind as being one of the following: fn,ne,e,se,s,sw,w,nwg. As shown in Figure 9.14, the device has eight outputs specifying the wind direction in a 1-out-of-8 code. A binary encoder is used to encode this wind direction as a 3-bit binary code. Encoders also exist for other output representations, such as BCD and Gray; their de nition and implementation are similar to those of the binary encoder, so that we do not discuss them further. As in the case of decoders, and for all other standard modules discussed later, limitations in the maximum number of connections to a module and number of gates in an implementation restrict the size of encoders that are available as standard modules (i.e., 16 inputs). Large encoders must be implemented as networks of standard encoders. 9.3 Priority encoders The binary encoder discussed in the previous section has the limitation that, at any given time, at most one input xi may have the value 1. In contrast, a priority encoder may have several inputs with the value 1. The output represents, in a binary code, the index of the highest priority input having the value 1. The priority is a xed ordering implemented by the encoder; usually, x2n 1 has the highest priority whereas x0 has the lowest. A high-level description of a priority encoder is 336 Chapter 9. Standard combinational modules Wind direction in unary code 0 1 0 n nw w sw s se ne e 0 0 0 0 2 3 4 5 BINARY ENCODER 1 Wind direction in binary code 0...
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