CSM51Ach9

CSM51Ach9 - 318 Chapter 9 Standard combinational modules In...

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Unformatted text preview: 318 Chapter 9 Standard combinational modules In this chapter, we present A set of widely used standard combinational modules. The speci cation of these standard modules. A gate network implementation for each of these standard modules. The main uses of these standard modules. The implementation of large modules as networks of smaller ones. Complex digital systems are implemented as modular networks. Although fully custom-designed modules are used in special cases, most frequently the systems are built using standard modules. These standard modules correspond to subfunctions that have been identi ed as useful for a large variety of applications, and have been made available as \o -the-shelf" and library components, that is, ready to use as part of a modular network. This approach is applicable at all levels of integration (msi, lsi, vlsi). The design of a system using standard modules consists of two steps: decompose the overall functionality of the system into subfunctions that can be mapped onto standard components; and interconnect the chosen standard components as a modular network. If the decomposition still produces complex subfunctions, a new level of decomposition is applied until the mapping of subfunctions onto standard components becomes feasible. 319 320 Chapter 9. Standard combinational modules E En y 0 0 1 2 n-Input Binary Decoder y 1 2 x y x 1 1 x n-1 n-1 n 2 -1 yn 2 -1 Figure 9.1: n-input binary decoder. In this chapter, we begin the study of standard modules by introducing a set of widely used combinational components, namely decoders, encoders, multiplexers, demultiplexers and shifters. We de ne the function of these modules, give high-level and binary-level descriptions, and indicate their basic use. We also describe how to construct networks of these standard modules. Other standard combinational and sequential modules are described in the following chapters. 9.1 Binary decoders An n-input binary decoder (see Figure 9.1) is a combinational system that has n binary inputs x = (xn 1; : : :; x0) and 2n binary outputs y = (y2n 1; : : :; y0). The input vector x can be considered as representing integers from 0 to 2n 1 in the radix-2 representation. At any given time, at most one binary output { say yi { is equal to 1 and all other outputs are equal to 0; yi = 1 indicates that the input bit-vector represents the integer i. That is, the module can be regarded as a code converter from the binary code to the 1-out-of-2n code. An additional input, called module enable E , is used to facilitate the implementation of network of decoders; when E = 0, all outputs from the module are equal to 0 (or they are in the high-impedance state for three-state outputs). A high-level description of an n-input binary decoder is Outputs 0 0 Inputs 9.1. Binary decoders 321 x = (xn 1; : : :; x0); xj 2 f0; 1g E 2 f0; 1g y = (y2n 1 ; : : :; y0 ); yi 2 f0; 1g 1 if (x = i) and (E = 1) 0 otherwise P Inputs: Outputs: Function: yi = n wherein x = j =01 xj 2j and i = 0; : : :; 2n 1 Example 9.1 The function of a 3-input binary decoder is described by the following table: E x2 x1 x0 x y7 y6 y5 y4 y3 y2 y1 y0 1000000000001 1001100000010 1010200000100 1011300001000 1100400010000 1101500100000 1110601000000 1111710000000 0----00000000 Each decoder output corresponds to a switching function having value 1 for exactly one assignment, so it can be represented by one minterm. Consequently, the binary speci cation is given by Inputs: x = (xn 1; : : :; x0); xj 2 f0; 1g E 2 f0; 1g Outputs: y = (y2n 1; : : :; y0); yi 2 f0; 1g Function: yi = E mi (x) ; i = 0; : : :; 2n 1 wherein mi (x) is the i-th minterm of the n variables x A gate network implementation consists of n not gates and 2n and gates with n + 1 inputs each. Example 9.2 The switching expressions describing a 2-input binary decoder are y0 = x01x00E y1 = x01x0E y2 = x1x00E y3 = x1x0E 322 Chapter 9. Standard combinational modules E y x 0 0 1 2 y x y y 1 3 Figure 9.2: Gate network implementation of a 2-input binary decoder. A gate network implementation of this binary decoder is shown in Figure 9.2. As a short-hand notation, a decoder module is denoted by y = dec(x; E ) For example, for a three-input decoder, y = dec((1; 1; 0); 1) = (0; 1; 0; 0; 0; 0; 0; 0) Uses A binary decoder is used whenever a set of values has been encoded using a binary code and they have to be separated, that is, decoded. Speci cally, a set of 2n elements can be encoded on n binary variables. Then, an n-bit decoder can be used to identify which element of the set has been encoded. Typical examples are decoding the operation code (opcode) in a computer instruction, or decoding the address (location) referenced when accessing a memory. up to 16 di erent operations can be speci ed. Part of the instruction execution process consists of determining the operation speci ed in the instruction. A binary decoder can be used for these purposes, as shown in Figure 9.3. Example 9.3 A computer instruction has an opcode eld of four bits, so that Figure 9.4), a 1-bit data input, a 1-bit data output, and one control input to 1 The notation 1K is used to denote 1024=2 Example 9.4 A 16K 1 memory module stores 16K1 words of 1 bit each. This module has a 14-bit address used to specify one particular word input (see 10 , so that 16K denotes 16384=2 14 . 9.1. Binary decoders OPCODE field Instruction Other fields 323 E=1 En 4-Input Binary Decoder 15 . . . 4 3 2 1 0 LOAD STORE ADD JUMP Decoded operations Figure 9.3: Operation decoding. specify a memory operation (read or write). The implementation of the module consists basically of two parts: an array of 16K binary cells, each storing one bit, and a binary decoder that selects one of the cells for a read or write operation. Due to its size, this decoder cannot be implemented with a gate network of the type shown in Figure 9.2; a network of decoders has to be used instead, as discussed later. Decoders also exist for other input representations. For example, decimal decoders have ten outputs for codes such as BCD and Excess-3; their de nition and implementation are similar to those of the binary decoder, so we do not discuss them further. An n-input binary decoder and an or gate can realize any switching function of n variables, so that these two components correspond to a universal set of combinational modules. This is a consequence of the de nition of a binary decoder: since the i-th decoder output corresponds to minterm mi (x), then the implementation of any sum of minterms is obtained by performing an or with the outputs of the decoder that correspond to the minterms in the expression. Moreover, several functions of the same variables can be generated with one decoder and with one or gate per function. 9.1.1 Binary decoder and or gate as universal set Example 9.5 Consider the combinational system described by the following table: 324 Chapter 9. Standard combinational modules Cell referenced when address is Data input 00000000000010 Data input Binary cell E=1 Address 14 RAM Module (2 14 x 1) Address 14 Binary Decoder 0 1 2 16383 Read/write Read/write Data output (a) (b) Data output cells. Figure 9.4: Random-access memory (RAM): a) module; b) addressing of binary x2 x1x0 z2 z1 z0 000 010 100 001 010 001 011 010 100 001 101 101 110 000 111 100 This system can be implemented using a three-input binary decoder and or gates, as shown in Figure 9.5 and described at the binary level as follows: (y7 ; : : :; y0) = dec(x2 ; x1; x0; 1) z2 (x2 ; x1; x0) = y1 y5 y7 z1 (x2 ; x1; x0) = y0 y3 z0 (x2 ; x1; x0) = y2 y4 y5 9.1.2 Decoder networks 9.1. Binary decoders E=1 En 325 0 1 y0 y1 Binary Decoder y 2 3 2 z2 x0 x 1 0 1 2 y3 y4 4 5 z1 x2 y5 y 6 z0 6 7 y7 Figure 9.5: Network in Example 9.5. Due to limitations in the maximum number of connections to a module and the number of gates in an implementation, standard modules implement decoders with a small number of inputs (i.e., four inputs). Larger decoders are often required but it is impractical to implement them as one module, so that decoders networks are used instead. We now discuss two approaches for the design of these networks: coincident decoding and tree decoding. Let us consider the implementation of an 8-input binary decoder using standard 4-input binary decoders. For these purposes, let us divide the 8-bit input vector (x7; x6; :::; x1; x0) into two four-bit subvectors, as follows: x = (xleft ; xright ) xleft = (x7 ; x6; x5; x4) xright = (x3 ; x2; x1; x0) The coincident decoder is built as illustrated in Figure 9.6, wherein each subvector is decoded by one 4-input decoder, producing the vectors y = (y15 ; : : :; y0 ) and w = (w15; : : :; w0). Then, every pair consisting of one output from each decoder is applied as input to one of 256 2-input and gates. The outputs from these gates correspond to the outputs from the 8-input decoder. Outputs are labeled by noting that x = 24 xleft + xright where x, xleft , and xright are the integers represented by x, xleft , and xright , respectively. Consequently, zi corresponds to the output from the and gate Coincident decoding 326 x7 x6 Chapter 9. Standard combinational modules x5 x4 x3 x2 x1 x0 0 E En 0 1 0 1 0 En 1 0 0 4-Input Binary Decoder ... 210 4-Input Binary Decoder . . .4 3 2 1 0 15 15 y 2 w 4 1 1 0 z 255 1 z 36 0 z0 Figure 9.6: 8-input coincident decoder. with inputs ys and wt , wherein i = 24 s + t For example, output z36 is obtained from the and gate whose inputs are y2 and w4 because 36 = 24 2 + 4. The external (network) enable input E is connected to the enable input to one decoder module, whereas the enable input to the other module is set to 1. Consequently, if E = 0 then all outputs from one decoder module are 0, resulting in zi = 0 for all i. As a generalization of this network, an n-input binary decoder is implemented by two (n=2)-input binary decoders and 2n and gates, as indicated in Figure 9.7. The input to decoder W is xright = (x n 1 ; : : :; x0), whereas the 2 input to decoder Y is xleft = (xn 1; : : :; x n ). The network enable input is 2 connected to the enable of one of the decoders (for example Y ). A functional description that captures the network shown in Figure 9.7 is y = dec(xleft ; E ) w = dec(xright ; 1) z = (and(y2n=2 1; w2n=2 1); : : :; and(ys ; wt); : : :; and(y0 ; w0)) Tree decoding 9.1. Binary decoders 327 x n/2-1 x0 1 En DECODER W w n/2 2 -1 wt w0 z0 y0 x n/2 x n-1 DECODER Y ys En y n/2 2 -1 E z n/2 2 s+t zn 2 -1 Figure 9.7: n-input coincident decoder. 328 Chapter 9. Standard combinational modules Another approach to the implementation of large decoders is a tree-decoder network. For this case, let us consider the implementation of a 4-input binary decoder using standard 2-input binary decoders. As in the coincident decoder, let us divide the 4-bit input vector into two 2-bit subvectors, as follows: x = (xleft ; xright ) xleft = (x3 ; x2) xright = (x1 ; x0) Based on this decomposition, we can build a two-level tree network which has one decoder in the rst level and four decoders in the second level, as depicted in Figure 9.8. xleft is decoded in the rst level whereas xright is decoded in the second level. The 16 network outputs are partitioned into four groups of four outputs each, where each group is produced by one decoder module. The operation is as follows: each output from decoding xleft enables one of the decoders in the second level; and the decoding of xright produces the corresponding output from the enabled decoder. For example, if x = (0; 1; 1; 0) then xleft = (0; 1) so that decoder DEC1 is enabled. Moreover, xright = (1; 0), which produces a 1 at output 2 of decoder DEC1, that is, at output 4 1 + 2 = 6. Note the essential role of the decoder enable input in the operation of this network. In general, an n-input decoder can be implemented by a two-level tree with one ( n )-input decoder in the rst level and 2n=2 ( n )-input decoders in the 2 2 second level, as depicted in Figure 9.9. A functional description that captures the network shown in Figure 9.9 is w = dec(xleft ; E ) z = (dec(xright ; w2n=2 1); : : :; dec(xright ; wt); : : :; dec(xright ; w0)) The tree-decoder network can be generalized to a multilevel tree. If n = rk, wherein k is the number of inputs to a decoder module, then k input variables are introduced at each level producing a tree of r levels. The number of decoder modules in such a case is 1 + 2k + 22k + : : : + 2(r 1)k = (2n 1)=(2k 1) For example, for n = 12 and k = 4, there are r = 3 levels and the number of modules is (212 1)=(24 1) = 273. 9.1. Binary decoders x3 x=6: 0 1 329 x2 1 0 DEC 2 1 0 x1 1 0 x0 Level 1 E En 3 0 0 1 0 1 0 DEC 3 En 1 0 DEC 2 En 1 0 DEC 1 En 1 0 DEC 0 En Level 2 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 0 z 15 0 0 0 z 12 0 0 0 0 z8 0 1 z 6 =1 0 0 z4 0 0 0 0 z0 Figure 9.8: 4-input tree decoder. The following table compares the two decoder networks just presented. Each network implements a 2k-input decoder using k-input decoder modules and 2-input and gates. Coincident Tree Decoder modules 2 2k + 1 2k and gates 2 { Load per network input 1 decoder input 2k decoder inputs (max) Fanout per decoder output 2k and inputs 1 enable input Number of module inputs 2k + 2 + 22k+1 1 + k + 2k + k2k (related to number of connections) Delay tdecoder + tAND 2tdecoder Example 9.6 A six-input decoder is implemented using coincident- and treedecoder networks, as illustrated in Figure 9.10. As shown in the following table, the coincident scheme requires two 3-input decoders and 64 two-input and gates. If the delay of decoders and and gates are 2d and d, respectively, then the total delay is 3d. On the other hand, the tree decoder requires nine decoder modules and its delay is equal to 4d. Comparison of decoder networks 330 Chapter 9. Standard combinational modules x x n-1 x left x n/2 right x0 x n/2-1 Level 1 E En DEC w n/2 2 -1 wt w0 En En DEC t DEC 0 En Level 2 n/2 DEC 2 -1 zn 2 -1 z 2 (n/2)t+s z0 Figure 9.9: n-input two-level tree decoder. E Decoder x0 x1 x2 0 1 7 z0 z1 E x1 x2 0 1 7 Decoder x0 0 1 7 z0 z1 z7 1 x4 x5 0 1 7 (a) z 63 Decoder x3 x4 x5 Decoder x3 Decoder 0 1 7 z 56 z 57 z 63 (b) decoder. Figure 9.10: Implementation of 6-input decoder. a) Coincident decoder. b) Tree 9.2. Binary encoders 331 Coincident 2 64 1 decoder input 8 and inputs 136 3d Tree 9 { 8 decoder inputs (max) 1 enable input 36 4d Decoder modules and gates Load per network input Fanout per decoder output Number of module inputs Delay As it can be inferred from the example above, the tree-decoder network is better than the coincident network in terms of the number of interconnections. Coincident-decoding, on the other hand, allows a reduction in the complexity of the connections from the generation of the decoding function to its use in other parts of the network. This is illustrated by the implementation of the system shown in Figures 9.11a and 9.11b, which consists of a 12-input decoder and an array of 4096 storage cells; each cell is selected by one output from the decoder. In the case of the tree network, 4096 lines go from the decoder to the array as depicted in Figure 9.11a. On the other hand, in the case of the coincident network, the and gates can be part of the array of cells so that just 128 lines are required (see Figure 9.11b). 9.2 Binary encoders A 2n-input binary encoder (see Figure 9.12) is a combinational system that has 2n binary inputs x = (x2n 1 ; : : :; x0) and n binary outputs y = (yn 1 ; : : :; y0 ). This module performs the inverse function of a decoder: it converts from the 1-out-of-2n code into a binary code. At any given time, at most one of the inputs { say xi { may be equal to 1 and all other inputs must be equal to 0; the output bit-vector represents, in a binary code, the index of the input with the value 1 (that is, i). An additional input and an additional output, called module enable E and module active A, respectively, are used to facilitate the implementation of encoders networks. The enable input has the same functionality as in the case of decoders, whereas output A indicates whether the module is \active" (that is, there is an input with value 1). A high-level description of a binary encoder is 332 Decoder Chapter 9. Standard combinational modules Cell array Binary cell E=1 0 1 2 0 1 2 Data input 12 Address Tree Decoder 4095 4096 lines from decoder to cell array Read/write 4095 Data output (a) Decoder E=1 Cell array 0 0 Data input 6 Binary Decoder 63 1 12 Address E=1 6 Binary Decoder 0 63 4095 Read/write 128 lines from decoder to cell array equivalent to coincident decoder (b) Modified binary cell Data output Figure 9.11: a) System with tree decoder. b) System with coincident decoder. 9.2. Binary encoders E En 333 x x 0 1 0 1 -Input Binary Encoder y 0 1 0 1 y n-1 n-1 xn 2 -1 n 2 -1 Ac A Figure 9.12: 2n -input binary encoder. Inputs: x = (x2n 1 ; : : :; x0); xi 2 f0; 1g, with at most one xi = 1 E 2 f0; 1g Outputs: y = (yn 1; : : :; y0); yj 2 f0; 1g A 2 f0; 1g i 0 1 A= 0 Function: y = if (xi = 1) and (E = 1) otherwise if (some xi = 1) and (E = 1) otherwise Pn 1 y j =0 j wherein y = 2j and i = 0; : : :; 2n 1 Example 9.7 The function of an 8-input binary encoder is given by the following table: 2 n Outputs Inputs y 334 Chapter 9. Standard combinational modules E x7 x6 x5 x4 x3 x2 x1 x0 y 1000000010 1000000101 1000001002 1000010003 1000100004 1001000005 1010000006 1100000007 1000000000 0--------0 y2 y1 y0 000 001 010 011 100 101 110 111 000 000 A 1 1 1 1 1 1 1 1 0 0 Notice that if xi = 1, then yj is 1 if the binary representation of i has a 1 in its j -th bit. Consequently, the binary speci cation of a n-bit encoder is: Inputs: x = (x2n 1 ; : : :; x0); xi 2 f0; 1g, with at most one xi = 1 E 2 f0; 1g Outputs: y = (yn 1; : : :; y0); yj 2 f0; 1g A 2 f0; 1g P P (xk ); Function: yj = E A=E j = 0; : : :; n 1 (xi); i = 0; : : :; n 1 wherein xk is included in the expression for yj if the j -th bit of the binary representation of k is 1. Example 9.8 The switching expressions describing a 8-input binary encoder are y0 y1 y2 A = = = = E E E E (x1 (x2 (x4 (x0 x3 x3 x5 x1 x5 x6 x6 x2 x7 ) x7 ) x7 ) x3 x4 x5 x6 x7 ) A gate-network implementation of this binary encoder is given in Figure 9.13. Uses A binary encoder is used whenever the occurrence of one of several disjoint events needs to be represented by an integer identifying the event. 9.3. Priority encoders x7 x6 x5 x4 x3 x2 x1 x0 335 E y0 y1 y2 A Figure 9.13: Implementation of an 8-input binary encoder. Example 9.9 A device determines the direction of the wind as being one of the following: fn,ne,e,se,s,sw,w,nwg. As shown in Figure 9.14, the device has eight outputs specifying the wind direction in a 1-out-of-8 code. A binary encoder is used to encode this wind direction as a 3-bit binary code. Encoders also exist for other output representations, such as BCD and Gray; their de nition and implementation are similar to those of the binary encoder, so that we do not discuss them further. As in the case of decoders, and for all other standard modules discussed later, limitations in the maximum number of connections to a module and number of gates in an implementation restrict the size of encoders that are available as standard modules (i.e., 16 inputs). Large encoders must be implemented as networks of standard encoders. 9.3 Priority encoders The binary encoder discussed in the previous section has the limitation that, at any given time, at most one input xi may have the value 1. In contrast, a priority encoder may have several inputs with the value 1. The output represents, in a binary code, the index of the highest priority input having the value 1. The priority is a xed ordering implemented by the encoder; usually, x2n 1 has the highest priority whereas x0 has the lowest. A high-level description of a priority encoder is 336 Chapter 9. Standard combinational modules Wind direction in unary code 0 1 0 n nw w sw s se ne e 0 0 0 0 2 3 4 5 BINARY ENCODER 1 Wind direction in binary code 0 1 2 1 0 0 0 0 6 7 Figure 9.14: Wind direction encoder. Inputs: x = (x2n 1; : : :; x0); xi 2 f0; 1g Outputs: y = (yn 1 ; : : :; y0); yj 2 f0; 1g Function: y= A= i 0 1 0 P if (xi = 1) and (xk = 0; k > i) and (E = 1) otherwise if (some xi = 1) and (E = 1) otherwise n wherein y = j =01 yj 2j and i; k 2 f0; 1; : : :; 2n 1g Example 9.10 The function of a 8-input priority encoder is given by the following table: E x7 x6 x5 x4 x3 x2 x1 x0 y2 y1 y0 A 1000000010001 10000001-0011 1000001--0101 100001---0111 10001----1001 1001-----1011 101------1101 11-------1111 1000000000000 0--------0000 9.3. Priority encoders E Lowest priority 337 z 0 0 En 0 1 x x 0 1 Priority Resolution z 1 1 1 -Input Binary Encoder 0 y 0 1 0 1 y n-1 n-1 xn 2 -1 Highest priority n 2 -1 n 2 -1 2 -1 n 2 -1 Ac A Figure 9.15: Priority encoder. A priority encoder can be implemented by two subsystems, as indicated in Figure 9.15. The rst is a priority-resolution subsystem, which changes to 0 all inputs with value 1 except the highest priority one, and the second is a binary encoder as the one discussed in the previous section. A high-level description of the priority-resolution subsystem is Inputs: x = (x2n 1 ; : : :; x0); xi 2 f0; 1g Outputs: z = (z2n 1 ; : : :; z0 ); zi 2 f0; 1g Function: zi = 1 if (xi = 1) and (xk = 0; k > i) 0 otherwise with i; k = 0; 1; : : :; 2n 1 The corresponding binary description of the function is given by the following set of switching expressions: zi = x02n 1 x02n 2 : : :x0i+1 xi ; i = 0; 1; : : :; 2n 1 Figure 9.16a depicts a priority resolution network implemented with and gates, in which output i requires a gate with 2n i inputs. Such an implementation is adequate for a small number of inputs but is impractical for larger modules due to the large gates required. Figure 9.16b shows an iterative implementation which is more suitable for a large number of inputs, although it 2 zn n Outputs Inputs y 338 Chapter 9. Standard combinational modules x0 c0 z0 x0 x1 x2 z0 z1 z2 x2 z3 x3 (a) Cell x1 c1 z1 x3 c2 z2 z3 (b) Figure 9.16: 4-bit priority resolution networks: a) parallel; b) iterative. has a large delay. This implementation is based on the replication of a cell which is described by the expressions ci 1 = ci xi zi = c0i xi An analysis by substitution shows that these expressions implement the priority resolution. Uses A priority encoder is used to select, according to a prede ned priority, one out of several events that can occur simultaneously, representing the selected event by an integer. For example, the processor in a computer system receives requests for attention by means of interrupt signals. Several of these signals can be active at the same time, being necessary to select one of them for service; this is done according to pre-established priorities. As shown in Figure 9.17, a priority encoder is used to identify the interrupting signal with the highest priority. Another typical use of a priority encoder is to determine the position of the leftmost (or rightmost) bit set to 1 in a bit-vector. Sometimes this operation is followed by a shift of the bit-vector so that there are no leading (trailing) zeroes (see Figure 9.18). 9.3. Priority encoders 339 Request lines E=1 Device A 1 lowest priority 0 En Highest priority 0 request Device B 0 PRIORITY ENCODER 1 0 PROCESSOR 1 1 Device C 1 2 Device D 0 highest priority 3 Ac A=1 Request present Figure 9.17: Resolving interrupt requests using a priority encoder. x 7 x 6 x 5 x 4 x 3 x2 x1 x 0 0 0 1 0 1 0 0 1 E=1 En PRIORITY ENCODER Ac 0 1 2 1 0 1 SHIFTER 1 0 1 0 0 1 0 0 (x shifted left 2 positions with 0s inserted into vacated positions) Figure 9.18: Detecting the leftmost 1 in a bit-vector and removing leading zeroes. 340 Chapter 9. Standard combinational modules E x0 x1 0 1 2 En x2 2 - Input Multiplexer Data inputs Data output z xn 2 -1 n 2 -1 n-1 n 0 s n-1 s0 Select inputs Figure 9.19: 2n-input multiplexer. A 2n-input multiplexer has 2n binary (data) inputs x = (x2n 1 ; : : :; x0), n binary control (select) inputs s = (sn 1; : : :; s0 ), a module enable input E , and one data output z (see Figure 9.19). The output of the multiplexer is equal to the data input selected by the control input. Speci cally, the values of the control variables s are interpreted as the binary representation of the integer s (in the range from 0 to 2n 1) and the output is equal to xs. A high-level description of a multiplexer is Inputs: x = (x2n 1 ; : : :; x0); xi 2 f0; 1g s = (sn 1 ; : : :; s0); sj 2 f0; 1g E 2 f0; 1g Outputs: z 2 f0; 1g Function: z = xs if E = 1 0 if E = 0 P 9.4 Multiplexers (selectors) n wherein s = j =01 sj 2j . Since the minterm mi (s) has value 1 only when s = i, a binary representation of the multiplexer function is given by the following switching expression: z=E X2 n 1 i=0 xi mi (s) wherein mi (s) is the i-th minterm of the n select inputs. 9.4. Multiplexers (selectors) x0 x x x 1 2 3 341 z E s 1 s 0 Figure 9.20: Gate implementation of 4-input multiplexer Example 9.11 The function of a 4-input multiplexer is described in tabular form as follows: E s1 s0 z 1 0 0 x0 1 0 1 x1 1 1 0 x2 1 1 1 x3 0--0 The corresponding switching expression is z = E (x0m0 (s1 ; s0) x1 m1 (s1 ; s0 ) x2m2 (s1 ; s0 ) x3 m3 (s1 ; s0)) = E (x0s01 s00 x1s01 s0 x2 s1 s00 x3s1 s0 ) This switching expression results in the gate-network implementation illustrated in Figure 9.20. A typical use of a multiplexer is selecting one of the bits of a bit-vector, and performing some action on the corresponding bit. Another typical use, depicted in Figure 9.21, is the placement of a multiplexer at the input of a functional unit that can operate with one of several operands; the multiplexer is used to select a particular operand. A 2n-input multiplexer can be used to implement any switching function of n variables, as follows: 9.4.1 Multiplexer as universal combinational module 342 R0 R1 Chapter 9. Standard combinational modules R0 R2 R3 R4 SelA 0 1 0 1 2 3 MUX A MUX B SelB A B For n-bit operands, Mux A and MuxB replicated n times and connected to the corresponding bit s of the input vectors. f FUNCTIONAL UNIT Example: SelA = 1, SelB = 2 Z = f(R1,R3) Z= f(A,B) Figure 9.21: Multiplexer: example of use. connect the input variables x to the select inputs of the multiplexer s; and set the data inputs to the multiplexer equal to the values of the function for the corresponding assignment of the select variables. Figure 9.22a illustrates a case with n = 3. Since any function of n variables can be implemented with a 2n -input multiplexer, this is a universal module. The number of data inputs to the multiplexer can be reduced if, in addition to the constants 0 and 1, one variable or its complement is connected to the data inputs. In this way, a 2n-input multiplexer can implement any function of n +1 variables. To illustrate this approach, consider the function f (x2 ; x1; x0) = one-set(1,2,4,6,7) shown in Figure 9.22a. To use variable x2 as a data input, the corresponding sum of products expression is transformed as follows: E (x2; x1; x0) = m(1; 2; 4; 6; 7) 0 (x0 x0) x0 (x1x0 ) x2(x0 x0 ) = x2 1 2 0 10 = x02 m1 (x1; x0) x02 m2 (x1; x0) x2 m0 (x1; x0) x2 m2 (x1; x0) = x2 m0 (x1; x0) x02 m1 (x1; x0) 1 X x2(x1x00 ) x2(x1 x0) x2 m3 (x1; x0) m2 (x1; x0) x2m3 (x1; x0) This decomposition can also be obtained from a K-map, as shown in Figure 9.22b. The corresponding implementation is given in Figure 9.22c. Example 9.12 Consider the implementation of a one-bit adder; its arithmetic function is described by 9.4. Multiplexers (selectors) 343 E=1 En 0 1 1 0 1 0 1 1 0 1 2 3 4 5 6 7 E=1 En 8 - Input Multiplexer x f = one-set(1,2,4,6,7) x’ 1 x 2 1 2 3 4 - Input Multiplexer 2 0 f = one-set(1,2,4,6,7) 2 1 2 1 0 x x 2 Select inputs 1 0 x 0 x 1 x 0 (c) (a) x0 x0 0 x2 1 0 1 x2 x’ 2 x2 1 1 0 1 x1 1 x1 (b) Figure 9.22: Implementation of f (x2 ; x1; x0) = one-set(1,2,4,6,7): a) 8-input multiplexer; b) K-map for 4-input multiplexer implementation; c) 4-input multiplexer. 344 Chapter 9. Standard combinational modules Inputs: a; b; cin 2 f0; 1g Outputs: z; cout 2 f0; 1g Function: z = (a + b + cin) mod 2 cout = 1 if (a + b + cin) 2 0 otherwise This function is described by the following table: a 0 0 0 0 1 1 1 1 b cin 00 01 10 11 00 01 10 11 z cout 00 10 10 01 10 01 01 11 This adder can be implemented using two 4-bit multiplexers, one for each output. We choose, among other possibilities, a and b as the control variables, and 0, 1, cin and c0in as the data inputs. For this choice, from the table we obtain the following switching expressions z = (a0 b0) cin = cinm0 (a; b) cout = 0 m0 (a; b) (a0b) c0in (ab0) c0in (ab) cin c0inm1 (a; b) c0inm2 (a; b) cinm3 (a; b) cin m1 (a; b) cin m2 (a; b) 1 m3 (a; b) The corresponding K-maps and implementation are shown in Figure 9.23. 9.4.2 Multiplexer trees A large multiplexer can be implemented as a multilevel network of multiplexer modules with fewer inputs, called a multiplexer tree. To illustrate this case, let us consider the implementation of a 16-input multiplexer using a tree of 4-input multiplexer modules, as depicted in Figure 9.24. The 16-input multiplexer network requires a select vector with four inputs, namely s = (s3 ; s2 ; s1 ; s0). Let us divide this vector into two subvectors, as follows: sleft = (s3 ; s2 ) sright = (s1 ; s0 ) 9.4. Multiplexers (selectors) 345 E=1 E=1 cin c’in 0 1 2 3 En 4-Input Multiplexer 0 0 1 En 4-Input Multiplexer z 2 cout 1 0 3 1 a b 1 0 z: cin cout : cin 0 a 1 0 0 1 b 1 0 a 0 0 0 1 1 1 b 0 1 1 cin a c’in c’in cin b a 0 cin cin 1 b Figure 9.23: Implementation of one-bit adder with 4-input multiplexers. 346 x 15 x 14 x 13 x 12 3 2 1 0 Chapter 9. Standard combinational modules x 11 x 10 x 9 x 8 3 2 1 0 x7 3 x6 2 x5 x4 1 0 x3 x2 x1 x0 1 En 1 0 1 En 1 0 1 En 1 0 1 En 1 0 3 2 1 0 MUX MUX MUX MUX s1 s0 0 1 x 13 x9 x5 x1 s3 s2 E 1 0 En 1 0 3 2 1 0 MUX z = x9 Figure 9.24: Tree implementation of a 16-input multiplexer. One of the subvectors (say sright , but either one can be used) is connected to the select inputs of all the modules at the rst level of the tree; consequently, the input at the same position is selected in each of these modules. That is, wj = x(4j +sright) ; 0 j 3 The other subvector (sleft in this case), is applied to the select inputs of the multiplexer module at the second level of the tree. This module selects one variable among the outputs from the modules at the rst level, so that z = wsleft By substitution, and taking into account that s = 4sleft + sright , it follows that z = x4sleft+sright = xs For example, as shown in Figure 9.24, if s = 9, then sleft = 2 and sright = 1. Consequently, the outputs from the multiplexers at the rst level are x1; x5; x9, and x13. From these, x9 is selected by the multiplexer in the second level. 9.5 Demultiplexers (distributors) A 2n -output demultiplexer is a combinational system with n control (select) inputs s = (sn 1; : : :; s0 ), one data input x, and 2n data outputs y = 9.5. Demultiplexers (distributors) E y En 0 1 0 1 2 347 y y Demultiplexer (DMUX) 2 Data input x Data outputs n 2 -1 n-1 0 yn 2 -1 s n-1 s0 Select inputs Figure 9.25: 2n-output demultiplexer. (y2n 1 ; : : :; y0) (see Figure 9.25). This module performs the inverse function of a multiplexer: it routes the input data to the output selected by the select variables; all other outputs are zero. An additional enable input E is used to facilitate the implementation of networks of demultiplexer modules. A high-level description of a demultiplexer is Inputs: x; E 2 f0; 1g s = (sn 1; : : :; s0 ) ; sj 2 f0; 1g Outputs: y = (y2n 1 ; : : :; y0) ; yi 2 f0; 1g x if (i = s) and ( Function: yi = 0 if (i 6= s) or (E E = 1) = 0) Pn where s = j =01 sj 2j and 0 i 2n 1. Example 9.13 The input-output function of a 4-output demultiplexer is shown in the following table: E s1 s0 s y3 y2 y1 y0 1000000x 101100x0 11020x00 1113x000 0---0000 348 Chapter 9. Standard combinational modules E x y 0 y1 y2 y3 s 1 s 0 Figure 9.26: Gate network implementation of a 4-output demultiplexer. At the binary level, a demultiplexer is described by the following switching expressions: yi = E x mi (s) ; 0 i 2n 1 A gate network implementation for a 4-output module is shown in Figure 9.26. Note the similarity with the implementation of the 2-input decoder shown in Figure 9.2. What is the di erence? The basic use of a demultiplexer is for transmitting the input data to one out of several outputs, under control of the select inputs. This is required, for example, when the output of a functional unit has to be distributed to one of several other units (see Figure 9.27), or when data is transmitted by a common channel and has to be distributed at the destination. 9.6 Shifters Simple shifter A simple shifter (see Figure 9.28) is a combinational system having an (n +2)- bit data input x = (xn ; xn 1; : : :; x0; x 1), an n-bit data output y = (yn 1 ; : : :; y0), and two one-bit control inputs: d (for the shifting direction) and s (for shift or no-shift). This system shifts the input data by one bit, either to the left or to the right depending on the value of d, or delivers the input data unchanged. An additional enable input E is used to facilitate the implementation of networks of shifter modules. 9.6. Shifters 349 Y DMUX 0 1 2 3 Sel S0 S1 S2 S3 0 1 2 3 MUX X For n-bit operands, Mux and Dmux replicated n times and connected to the corresponding bit s of the input/output vectors. f FUNCTIONAL UNIT Z= f(X) Figure 9.27: Demultiplexer: example of use. 350 Chapter 9. Standard combinational modules xn x n-1 xi x 0 x -1 n n-1 i 0 -1 E s d shift/ no shift n-bit Simple Shifter left/ right n-1 i 0 y n-1 yi (a) y0 xn x n-1 x i+1 x 1 x 0 x -1 s= YES d= RIGHT shift/ no shift left/ right E=1 y n-1 yi (b) y0 x n x n-1 x n-2 x i-1 x 0 x -1 s= YES d= LEFT shift/ no shift left/ right E=1 y n-1 yi (c) y0 Figure 9.28: n-bit simple shifter: a) block diagram; b) right shift; c) left shift. 9.6. Shifters 351 A high-level description of a simple shifter is Inputs: x = (xn; xn 1; : : :; x0; x 1) ; xj 2 f0; 1g d 2 fright; leftg s 2 fyes; nog E 2 f0; 1g Outputs: y = (yn 1 ; : : :; y0 ) ; yj 2 f0; 1g (d = left) and (s = yes) and (E = 1) (d = right) and (s = yes) and (E = 1) yi = > (s = no) and (E = 1) > : (E = 0) for 0 i n 1. Note y0 = x 1 that in the left shift, whereas yn 1 = xn in the right shift. Depending on the values of these inputs, some special shift cases are as follows: xi 1 xi+1 xi 0 x1 = xn = 8 < : 8 < : Function: 8 > > < if if if if 0 1 xn 0 1 x0 left shift with 0 insert left shift with 1 insert 1 left rotate right shift with 0 insert right shift with 1 insert right rotate Example 9.14 The operation of a 4-input shifter is as follows: Data x4 x3 x2 x1 x0 x 1 100110 No shift no { 0011 Right shift yes right 1001 0110 Left shift yes left y3 y2 y1 y0 s Figure 9.29 illustrates a gate-based implementation and a multiplexer-based implementation of a simple shifter. For these implementations, the coding of the control variables is s d 0 no 0 right 1 yes 1 left Control d 352 Chapter 9. Standard combinational modules xn d LEFT RIGHT x n-1 x n-2 x1 x0 x -1 E s NO SHIFT y n-1 (a) xn x n-1 x n-2 x1 y0 x0 x -1 E En 3 1 0 2 1 0 En 3 1 0 2 1 0 MUX MUX s d y n-1 (b) y0 Figure 9.29: Implementation of a simple shifter: a) with gates; b) with multiplexers. 9.6. Shifters x n+p-1 x n x n-1 x 0 x -1 x -p 353 s log(p+1) distance n-bit p-Shifter left/right En E d y n-1 y0 Figure 9.30: n-bit p-shifter. p-shifter A p-shifter is a generalization of the simple shifter, in which a (n +2p)-bit data input x = (xn+p 1 ; : : :; xn; xn 1; : : :; x0; x 1; : : :; x p) is shifted 0; 1; : : :; p positions, either to the left or to the right. The shift distance, that is the number of positions shifted, is speci ed by a control input s; the shift direction is speci ed by input d. The subvectors (xn+p 1 ; : : :; xn) and (x 1 ; : : :; x p) provide the additional bits required for the shifts (see Figure 9.30). An additional enable input E is used to facilitate the implementation of networks of shifter modules. A high-level description of a p-shifter is Inputs: x = (xn+p 1 ; : : :; xn; xn 1; : : :; x0; x 1; : : :; x p ) ; xj 2 f0; 1g s 2 f0; 1; :::; pg d 2 fleft; rightg E 2 f0; 1g Outputs: y = (yn 1 ; : : :; y0 ) ; yj 2 f0; 1g Function: xi s yi = : xi+s 0 0 8 < if (d = left) and (E = 1) if (d = right) and (E = 1) if (E = 0) in1 Barrel shifter A p-shifter can be implemented by means of a barrel shifter. This implementation is based on the fact that any shift distance s can be obtained by a sequence of shift distances, each of them being either 0 or a power of 2. This 354 Chapter 9. Standard combinational modules results from the binary representation of the distance s by the bit-vector s, such that r1 X s = sj 2 j ; 0 s p where p = 2 1. Therefore, a network of r stages, in which the j -th stage shifts a distance of 0 or 2j , implements a (2r 1)-shifter (see Figure 9.31). Each stage is implemented by n + 2p 3-input multiplexers, which are controlled by the corresponding sj bit and the direction bit d. The delay of a barrel shifter is proportional to the number of stages, that is, r = log2(p + 1). r j =0 the data input vector is shifted in only one direction (either left or right). Figure 9.32 depicts a 4-bit right 3-shifter implemented using multiplexers. Note that a left 3-shifter can be implemented using this right shifter just by reversing the order of the elements in the input vector. Typical uses of shifters include Alignment of a bit-vector. For example, oating- point addition requires the exponents to be equal before adding the mantissas; adjusting the value with the smaller exponent implies shifting the corresponding mantissa to the right. Removal of the leading (or trailing) bits of a vector. For example, in arithmetic operations that require normalization of an operand, the leading zeros are eliminated by shifting. Performing multiplication or division by a power of two. Extracting a subvector from a bit-vector, using a shifter instead of a selector. Large shifters are implemented by networks of shifter modules. The design of networks of unidirectional p-shifters is considered in Exercise 9.21. Unidirectional shifters A unidirectional shifter is a simpli cation of a bidirectional shifter in which Uses 9.7 Implementation of modules The modules we present in this chapter, as well as those of Chapters 9, 10, and 11, are implemented either as individual chips or as part of more complex chips. Although their functionality has been used since the early digital 9.7. Implementation of modules 355 x d n+2p s0 0 or 1 SHIFT Stage 0 s1 0 or 2 SHIFT Stage 1 s2 0 or 4 SHIFT Stage 2 s3 0 or 8 SHIFT Stage 3 y Figure 9.31: Barrel shifter for p = 15. 356 x6 x5 x4 x3 Chapter 9. Standard combinational modules x2 x1 x0 E En 3 1 0 2 1 0 En 3 1 0 2 1 0 En 3 1 0 2 1 0 En 3 1 0 2 1 0 MUX MUX MUX MUX s1 s0 y3 y2 y1 y0 Figure 9.32: Multiplexer implementation of a 4-bit right 3-shifter. systems, they became known as standard modules when they were integrated, rst into separate cards and then into separate chips. Each manufacturer of digital circuits developed a family of these modules, the most popular being the 74-series. Modules of this series are available as single chips and as \macros" in most libraries of cells for the design of VLSI chips. The availability of these chips and macros allows a designer to use them freely in the design of complex systems. The implementation of the standard modules in terms of gates and transistors depends on the technology and on characteristics such as delay and area. The chip manufacturers and the designers of cell libraries perform implementations optimized for their particular technology and compatible with the characteristics of other modules and cells. As a consequence, the networks of gates we show in this and successive chapters are conceptual and might not be optimal for a particular library. 9.8 Further readings A classical text covering the design with modules discussed in this chapter is Digital Design with Standard MSI and LSI by T.R. Blakeslee, 2nd ed., Wiley & Sons, 1979. Another example of a textbook covering in detail this subject is Digital Systems and Hardware/Firmware Algorithms by M. Ercegovac and T. Lang, Wiley & Sons, 1985. The 74-series of modules is discussed in detail in Digital Design: Principles and Practices by J.F. Wakerly, Englewood Cli s, NJ: Prentice-Hall, 1994. Additional details about implementation and use can be found in numerous literature available from manufacturers of integrated circuits. 9.9. Exercises 357 9.9 Exercises Decoders and encoders Ex. 9.1 Implement 10-output (decimal) decoders using nand gates for a) a 2-out-of-5 code; b) a 4-bit Gray code; c) a 2-4-2-1 code. The corresponding codes are de ned in Chapter 2. Ex. 9.2 Implement a BCD decoder using one Excess-3 decoder, one 2-input binary decoder, one 2-input nor gate, and one inverter. Make sure that the Excess-3 decoder is disabled when the input is out of range for that code. Ex. 9.3 Implement the odd and even parity functions of four variables using a 4-input decoder and or gates. Ex. 9.4 The coincident decoding approach can be extended to the case in which the input vector is divided into more than two subvectors. If n = rk, where k is the number of inputs to a decoder module, then the coincident scheme consists of r decoders and 2n r-input and gates. Design a coincident decoder for n = 12 and k = 4. Ex. 9.5 Answer the following questions: a) How many 4-input decoders are needed to implement a 20-input decoder using tree decoding? How many levels will there be? b) How many 4-input decoders are needed to implement a 20-input decoder if coincident decoding is used (see Exercise 9.4)? How many and gates will be needed? Ex. 9.6 Using and and or gates, implement a 10-input encoder for a) the 2-out-of-5 code; b) the Gray code; c) the Excess-3 code. These codes are de ned in Chapter 2. Ex. 9.7 Analyze the network depicted in Figure 9.33 and show that it implements a priority encoder. Give a high-level speci cation. Note that in this implementation, inputs and outputs are complemented with respect to the normal description of the priority encoder. That is, the output encodes the highest priority 0, and the encoding is the binary representation of the corresponding integer with each bit complemented. 358 Chapter 9. Standard combinational modules I1 I2 A I3 I4 I5 B I6 I7 C I8 I9 D Figure 9.33: Network for Exercise 9.7. 9.9. Exercises Display of the digit 5 359 1 0 1 0 0 1 2 3 BCD-toseven-segment display converter b 0 a 0 f g e d c 0 1 0 0 1 a f b g e d c A segment is made dark by applying 0 to it Figure 9.34: BCD-to-seven-segment decoder and display for Exercise 9.8. Ex. 9.8 Specify and implement code converters for a) BCD to 7-segment code (the 7-segment code can be inferred from Figure 9.34); b) 4-bit binary to 4-bit Gray code; c) BCD to 2-out-of-5 code. Perform two implementations for each: a decoder plus or gates, and a decoder plus an encoder. Ex. 9.9 Using a 3-input binary decoder and a 8-input binary encoder, implement a code converter from the 3-bit Gray code into the 3-bit binary code. Ex. 9.10 Specify a cyclic priority encoder that has eight data inputs and three binary control inputs. The control inputs determine which of the data inputs is highest priority. The priority diminishes cyclically. For example, if input 5 is highest priority, then the order is 5,4,3,2,1,0,7,6. Design a network that implements this function and consists of a priority encoder, a 3-bit binary adder, and a shifter. Ex. 9.11 Design a combinational network that has a 3-bit input x representing the digits 0 to 7, and a 3-bit output y representing the same set of integers. The function of the system is y = (3x) mod 8. Use a decoder and an encoder. Ex. 9.12 Analyze the network shown in Figure 9.35 and show that it implements a 64-input binary encoder. 360 Chapter 9. Standard combinational modules ’1’ x 0 En ENCODER x 7 Ac A0 ’1’ x 8 En ENCODER y 2 y 0 y 1 x 15 Ac A1 ’1’ En ENCODER y y y 3 4 5 ’1’ x 56 En ENCODER Ac A x 63 Ac A7 Figure 9.35: Implementation of a 64-input encoder. 9.9. Exercises xn 2 -1 361 xn k 22 xk 2 -1 x0 1 En 1 En 1 En MUX s0 MUX MUX s n/2-1 s n/2 E En MUX s n-1 z Figure 9.36: Network for Exercise 9.14. multiplexer? How many levels will there be? Ex. 9.14 In general, a 2n-input multiplexer can be implemented by a two-level tree network of 2n=2-input multiplexer modules, as shown in Figure 9.36. This scheme can be generalized to the case in which there are r levels; assuming that n = rk, determine how many modules are needed. Ex. 9.15 Implement the function f (a; b; c; d) = one-set(1,3,4,9,14,15) using a) an 8-input multiplexer; b) a 4-input multiplexer and nor gates (use inputs a and b as select inputs to the multiplexer, the nor gates for functions f (0; 0; c; d), f (0; 1; c; d), f (1; 0; c; d) and f (1; 1; c; d), and connect the outputs of these networks to the corresponding data input to the multiplexer). Ex. 9.16 Implement an 8-input multiplexer using a 3-input decoder and nand gates. Multiplexers and Demultiplexers Ex. 9.13 How many 4-input multiplexers are needed to implement a 256-input Shifters Ex. 9.17 Implement a) an 8-bit simple shifter using multiplexers; 362 Chapter 9. Standard combinational modules b) an 8-bit bidirectional 3-shifter using multiplexers. Ex. 9.18 Implement a left 3-shifter using a right 3-shifter. Ex. 9.19 Design a 32-bit 3-shifter using four 8-bit 3-shifters to implement a) a left shifter; b) a bidirectional shifter. Ex. 9.20 Analyze the network shown in Figure 9.37. Can it be used for shifting? Rotation? Bidirectional? How many positions? Ex. 9.21 a) Design a 12-bit right 3-shifter using 4-bit right 3-shifter modules. b) Show how to implement large shifters as networks of standard k-bit/pshifter modules; for simplicity, consider only the case of a unidirectional right-shifter. How many k-bit/p-shifter modules are needed to implement a n-bit unidirectional p-shifter? Networks of modules Ex. 9.22 Analyze the network shown in Figure 9.38 and design a gate network using and, or, xor and nor gates that implements the same function. (Hint: z = 1 if the inputs to the decoder and the multiplexer are identical. Implement an equality comparator using xor gates and one nor.) Ex. 9.23 Show that the network shown in Figure 9.39 can be used to transmit the vector x in a serial manner and to store it in register y . level description of its function. (Hint: Reduce the number of states and draw a state diagram). Is this a reasonable implementation for this function? If not, obtain a better canonical implementation. Ex. 9.24 Analyze the sequential system shown in Figure 9.40. Give a high- Ex. 9.25 Analyze the controller depicted in Figure 9.41. Give a state diagram. Ex. 9.26 Two digital systems use unconventional codes to represent integers between 0 and 15 as follows: System A represents integer n as p = 3n mod 16, and p is represented by the vector p in binary code. For example, for n = 3, p = 9 mod 16 = 9 = (1001) and for n = 13, p = 39 mod 16 = 7 = (0111). 9.9. Exercises 363 x7 x6 x5 x4 x3 x2 x1 x0 Stage 0: Shift 0 or 1 s0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 2-input multiplexers 2-input multiplexer Stage 1: Shift 0 or 2 s1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 2-input multiplexers Stage 2: Shift 0 or 4 s2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 2-input multiplexers y7 y6 y5 y4 y3 y2 y1 y0 Figure 9.37: Network for Exercise 9.20. 364 Chapter 9. Standard combinational modules ’1’ ’1’ En En 0 0 1 ’1’ En a’ ’1’ a Binary Decoder ’0’ 0 1 1 w 2 3 4 5 6 2 3 4 5 6 7 2 1 0 2 1 0 2 3 1 0 MUX MUX z b c d e 7 f g h Figure 9.38: Network for Exercise 9.22. E1 x0 x1 En 0 1 E2 En 0 1 y0 y1 MUX DEMUX x7 a b c 7 2 1 0 2 1 0 7 y7 Figure 9.39: Network for Exercise 9.23. 9.9. Exercises 365 ’1’ En 0 ’1’ En 1 0 1 2 3 S0 S1 S2 S3 S1 S3 1 MUX 2 3 1 0 0 x State Register ’1’ S3 S0 S2 S2 S3 0 1 En Y 0 y 0 Binary Decoder z Y y 1 MUX 2 3 1 0 1 x Y 2 y 2 CLK ’1’ S0 S1 0 1 En MUX S0 2 3 1 0 Figure 9.40: Network for Exercise 9.24. 366 initial S0 go S3 S4 S1 dist < 10 count = 3 S2 S1 dist > 10 dist < 10 count = 3 S5 ’0’ S1 0 Chapter 9. Standard combinational modules ’1’ En ’1’ State Register Y 0 En 0 S0 S1 1 clearcount check turnleft countup move stop y 0 0 Binary Decoder Binary Encoder 1 0 S2 2 S3 3 4 5 6 7 S4 S5 2 3 4 5 6 7 Y 1 1 y 1 1 Y 2 2 y 2 2 CLK Figure 9.41: Network for Exercise 9.25. System B represents integer m as q = 7m mod 16, where the code of q is binary. For example, for m=6, q = 42 mod 16 = 10 = (1010). To link systems A and B , a combinational system is needed to convert an integer between 0 and 15 in the A code to the corresponding B code. Design such a system using a) one 8-input multiplexer and one 2-input xor gate; b) one 4-input decoder and one 16-input encoder. ...
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This note was uploaded on 03/26/2010 for the course CS 187154200 taught by Professor Ercegovac,m.d. during the Winter '09 term at UCLA.

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