CSM51Ach12

CSM51Ach12 - 450 Chapter 12 Programmable modules In this...

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Unformatted text preview: 450 Chapter 12 Programmable modules In this chapter we present: The speci cation of programmable combinational and sequential modules (psa, rom, pga). The way the modules are programmed. Examples of uses of these modules. The last chapters have discussed modules that realize speci c functions, and the implementation of systems using those modules. The resulting implementations are characterized by being \rigid" in the sense that any changes in the speci cation (i.e., the functionality) of the system requires a redesign. An alternative to get exibility in an implementation consists of using programmable modules. These modules have a standard ( xed) structure and are customized for a particular function either at the last stages of fabrication, or when the module is incorporated as part of a system, or when the system is activated (powered up). In Chapter 5 we already described two programmable combinational modules: plas and pals. As mentioned there, programmable modules have become quite popular but, in spite of the advantages arising from their exibility, they have not replaced xed-function standard modules in all applications because they are somewhat more expensive and slower than a wellsuited xed-function module; moreover, in the case of vlsi implementations, programmable modules occupy a larger area than the xed-function counterparts. In this chapter, we present other types of combinational and sequential programmable modules; we describe their speci cation, their implementation, and how they are used in networks for the implementation of more complex 451 452 inputs Chapter 12. Programmable modules outputs x n PLA present state next state z k State register p y Y p PSA clk Figure 12.1: Programmable sequential array (psa). digital systems. The programmable modules discussed are Programmable Sequential Arrays (psa), Read-Only Memories (rom), and Programmable Gate Arrays (pga). We also give an overview of the advantages and limitations of programmable modules. An -input, 2 -state, -output programmable sequential array (psa) is a module that provides a canonical implementation of a sequential system with 2 states. A high-level description of this module is n p k p 12.1 Programmable sequential arrays (psa) Inputs: Outputs: State: x E z s =( =( =( 2 f0 1g ; zk pn xn 1; : : : ; x0 ) ; ; xi 2 f0 1g ; ; ; 1; : : : ; z0 1; : : : ; p0 ) ) zi pi ; 2 f0 1g 2 f0 1g r Function: not-and-or or not-or-and implementation of + switching functions, with maximum terms total k p As depicted in Figure 12.1, a psa consists of a pla with ( + ) inputs and ( + ) outputs, and a register with binary cells. The psa module is an extension of the pla module used for combinational systems: the register is used for storing the state, whereas the and and the or arrays are used for implementing the state transition and output functions. n p k p p 12.1. Programmable sequential arrays (psa) 453 Implementation of sequential systems using psas The implementation of a sequential system using a psa follows the procedures described in Chapter 8, as illustrated by the following example. Example 12.1 A sequence generator has one binary input and a number in the set f0 1 3 6 7 10 14g as output. The system generates one of two predened sequences selected by , as de ned by the following high-level speci cation: x ; ; ; ; ; ; x Inputs: Outputs: x z 2 f0 1g 2 f0 1 3 6 7 10 14g ; ; ; ; ; ; ; Function: The transition and output functions are = 0 : = 0 ! 10 ! 14 ! 7 ! 0 = 1 : = 1 ! 10 ! 3 ! 6 ! 1 The output sequence changes only at the end of each four-cycle period, but can change in any clock cycle. x z x z x In words, each output sequence consists of four values, with a period of four clock cycles. The corresponding time behavior is shown in Figure 12.2. This sequence generator is implemented using a psa module with a 5-bit state register. Four bits of the state are labeled with the corresponding output value; for simplicity, we use the radix-2 representation of the output integer as the label for those four bits. Thus, the binary speci cation of the output sequence is x x =0 : =1 : z z = 0000 ! 1010 ! 1110 ! 0111 ! 0000 = 0001 ! 1010 ! 0011 ! 0110 ! 0001 k In addition, input is used as the fth state bit, which we call (sequence control); this bit is updated at the end of each sequence (every four clock cycles), as follows: ( ) if ( ) = 3 ( + 1) = ( ) otherwise or 14 x kt xt kt st Consequently, the state is = ( 4 3 2 1 0) = ( 3 2 1 0). The system is initialized to = 0 and = 0. The corresponding transition function, in which represents the present state part ( 3 2 1 0) and corresponds to the next state part ( 3 2 1 0), is s s ;s ;s ;s ;s k; y ; y ; y ; y k y y y ;y ;y ;y Y Y ;Y ;Y ;Y 454 Chapter 12. Programmable modules CLK z3 z2 z1 z0 State 01 00 01 00 1 1 1 0 0 1 1 1 0 10 14 7 0 10 14 7 (a) Case x = 0 CLK z3 z2 z1 z0 State 01 00 01 10 0 0 1 1 0 1 1 0 1 10 3 6 1 10 3 6 (b) Case x = 1 Figure 12.2: Timing sequences in Example 12.1. 12.2. Read-only memories (rom) 455 k 0 1 3 6 7 10 14 y y k =0 10 0 0 14 7 Y ; ; ; =1 10 6 1 1 3 k k x k k k x K States corresponding to 2 f2 4 5 8 9 11 12 13 15g are don't care states. The corresponding minimal switching expressions are 00 0 0 0 = 32 321 1 32 32 00 0 3= 2 1 0 = 210 30 2 0 1= 3 2 0= 3 2 32 The implementation using a psa module is shown in Figure 12.3. From Example 12.1, it follows that all systems described in Chapter 8 can be implemented using psa modules, subject to restrictions in the size of these modules. ; ; ; ; ; K xy y y xy y y ky ky y ky y Y yk Y yyy y y yk Y Y yk yk yy A2 read-only memory (see Figure 12.4) is an array of 2 rows which contains vectors of -bits holding constant (prede ned) values. The input variables = ( 1 0) correspond to the memory address, which is used to select one particular row of this array; the selected row is made to appear at the output = ( 1 0). In other words, a read-only memory corresponds to a tabular representation of the combinational system in which the input bit-vector is used to identify which row in the array is accessed. The contents of the rows are frequently referred to as words. These modules usually provide three-state outputs and a module-enable input to facilitate the design of multimodule rom networks. A high-level speci cation of a rom is Inputs: =( 1 2 f0 1g 0) 2 f0 1g Outputs: =( 1 2 f0 1g 0) n k n k n x xn ; : : :; x z zk ; : : :; z E x xn ; ; : : :; x ; xi ; E z zk ; : : :; z ; zi ; 12.2 Read-only memories (rom) Function: z = rom( ) wherein rom is a 2 x n k table 456 Chapter 12. Programmable modules (from state register) x k y 3 y 2 y 1 y 0 -- programmable connection -- connection made 1 2 3 4 y’ 5 6 y 7 8 yy 9 10 11 12 13 14 15 16 17 18 32 210 1 2 y’ 3 yk 2 y’ y y y’ k’ 2 y k’ 3 yk 3 xy y 32 x y’3y’2y1 k y’1 k y’3 y2 k y3 y’2 9 next state K CLK 8 7 6 5 4 3 2 1 Y 3 Y 2 Y 1 Y 0 STATE REGISTER k y 3 y2 y1 y0 present state z 3 z 1 2 output z z 0 Figure 12.3: psa implementation in Example 12.1 12.2. Read-only memories (rom) E En 457 x0 Address Inputs x1 x n-1 2n X k ROM z k-1 z0 Outputs Figure 12.4: Read-only memory (rom.) Example 12.2 Given the 8 4 rom with the contents shown below, for input x = (0 1 0), the output is = (0 1 1 1). ; ; z ; ; ; Address Contents 010 011 100 101 110 111 000 001 x 0111 1000 0000 1111 1111 1011 1011 1101 z Figure 12.5 depicts an implementation of a 4 4 rom module. It consists of a decoder and a nor array. Note that this implementation is similar to that of a pla in which the rst nor array is replaced by a decoder, so that the programmability is restricted to the second nor array. Since the decoder implements all minterms of the variables, the rom does not have the limitation in the number of product terms that is inherent to the pla. On the other hand, the decoder occupies more area than the restricted and array of the pla. 458 Chapter 12. Programmable modules E x1 x0 1 1 1 1 0 0 0 1 1 0 1 0 1 z3 z2 z1 z0 0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 NOR Array Vdd pull-up devices Gnd - - Z (a) ZZZ 0 0 1 0 1 word 0 Gnd x0 x1 0 Binary decoder 1 1 1 0 0 word 1 1 2 word 2 1 0 1 1 Gnd word 3 1 0 3 0 0 E enable three-state buffers z3 (b) z2 z1 z0 Figure 12.5: mos implementation of a 4 4 read-only memory: a) the function; b) the circuit. ...
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