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select_ch8_2

# select_ch8_2 - Solutions Manual Introduction to Digital...

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Unformatted text preview: Solutions Manual - Introduction to Digital Design - November 2, 2000 Exercise 8.8 129 We need a 3-bit vector to represent the six states and a 2-bit vector to represent the output. Let us de ne the following encoding: y2y1y0 State 000 001 010 011 100 101 A B C D E F z1z0 00 01 10 a b c From the state table and the encoding we get the following K-maps. y0 y0 y0 1 1 1 1 0 0 0 0 0 0 1 y2 1 x Y2 : 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 y2 0 x Y1: 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 y2 0 x Y0 : y0 0 1 1 1 0 1 y1 0 y2 0 y0 0 0 0 0 1 0 y1 0 y2 1 y1 x z1 : 0 x z0 : y1 y1 Y0 = y0 Y1 = x y2y1y0 + x y1y0 + xy2y0 + xy1y0 Y2 = x y2y0 + x y1y0 + xy2y0 + xy2y1y0 z1 = y2y0 + xy0 z0 = x y1y0 + y2y0 + xy0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The corresponding switching expressions are The sequential network is shown in Figure 8.8 on page 130. 130 x’ y2 y0’ x’ y1 y0 x y2 y0 x y2’ y1’ y0’ x’ y2’ y1’ y0 x’ y1 y0’ x y2 y0’ x y1 y0 Solutions Manual - Introduction to Digital Design - November 2, 2000 Y2 Y1 Y0 y0’ y2 y2’ y1 y1’ y0 y0’ CK y2 y0 x y0 x’ y1 y0 y2 y0’ x y0’ z1 z0 Figure 8.8: Sequential network for Exercise 8.8 136 Exercise 8.12 Solutions Manual - Introduction to Digital Design - November 2, 2000 The state diagram for this sequential network is presented in Figure 8.13, for the case of receiving least signi cant bit and most signi cant bit rst. In each transition we use a pair of bits representing bits from input A (a(t)) and B (b(t)), respectively. The system output is the same as the state coding used. 00,11,10 10 EQUAL GREATER 00,11 01 01 LEAST SIGNIFICANT BIT FIRST 10 SMALLER 00,11,01 10 EQUAL GREATER 00,11 01 MOST SIGNIFICANT BIT FIRST SMALLER Figure 8.13: Serial Binary Magnitude Comparator, Exercise 8.12 For both implementation we need three states, coded as: State (y1 ; y0) EQUAL (A = B ) 00 GREATER (A > B ) 01 SMALLER (A < B ) 10 (a) Least-signi cant bit rst: In this case the transition table is: PS Inputs (a(t),b(t)) 00 01 10 11 00 00 10 01 00 01 01 10 01 01 10 10 10 01 10 NS (Y1 ; Y0) Solutions Manual - Introduction to Digital Design - November 2, 2000 We can see from the table that: 137 Y1 = y1(a(t) b(t)) + a(t) b(t) Y0 = y0(a(t) b(t)) + a(t)b(t) 0 0 0 0 The network is presented in Figure 8.14. Mem. Cell Y1 y1 a(t) b(t) y0 Y0 y1 y0 CK Figure 8.14: Serial Binary Magnitude Comparator, Exercise 8.12 (a) (b) Most-signi cant bit rst: In this case the transition table is: PS Inputs (a(t),b(t)) 00 01 10 11 00 00 10 01 00 01 01 01 01 01 10 10 10 10 10 NS (Y1 ; Y0) The new expressions are: Y1 = y1 + y0a(t) b(t) Y0 = y0 + y1a(t)b(t) 0 0 0 0 These expressions are easily implemented using gates. 148 Exercise 8.19 Solutions Manual - Introduction to Digital Design - November 2, 2000 The expressions for the ip- op inputs and for the output are JA = 1 KA = 1 JB = QC KB = 1 JC = QB KC = 1 z = QA QB QC The sequential network does not have any input; therefore, the state register changes in each clock pulse depending only on the previous state. The transition table is 0 0 0 0 QA (t)QB (t)QC (t) PS 000 001 010 011 100 101 110 111 JA(t)KA(t) JB (t)KB (t) JC (t)KC (t) QA(t + 1)QB (t + 1)QC (t + 1) 11 11 11 11 11 11 11 11 11 01 11 01 11 01 11 01 01 01 11 11 01 01 11 11 110 100 101 100 010 000 001 000 FF inputs NS Output z(t) 1 0 0 0 0 0 0 0 Let us de ne the following encoding: QAQB QC state 000 001 010 011 100 101 110 111 A B C D E F G H The resulting transition table is PS A B C D E F G H Let us try to reduce the number of states: P=1 1 () NS G E F E C A B A z 1 0 0 0 0 0 0 0 2 A 2 ( B; C; D; E; F; G; H ) 2222121 Solutions Manual - Introduction to Digital Design - November 2, 2000 3 11 32333 3 1 P3 = (A) (F;2H ) (C) (B; D;4E; G) 4 11 2 4434 34 5 1 P4 = (A) (F;2H ) (C) (E) (B; D; G) 5 11 2 3 445 345 1 P5 = (A) (F;2H ) (C) (E) (G) (B;6D) 5 11 2 3 6 44 1 P2 = (A) ( 149 F; H ) 2 ( B; C; D; E; G) 3 P6 = P5 = f(A); (E ); (C ); (F; H ); (G); (B; D)g The reduced state table is PS (A) = S0 (E ) = S1 (C ) = S2 (F; H ) = S3 (G) = S4 (B; D) = S5 The state diagram is shown in Figure 8.23. S0/1 S1/0 S2/0 NS z S1 1 S2 0 S3 0 S0 0 S5 0 S1 0 S5/0 S4/0 S3/0 Figure 8.23: State diagram for Exercise 8.19 The network in its equilibrium state produces a 1 every six clock pulses, that is, it implements a modulo-6 frequency divider. 154 Exercise 8.22 Solutions Manual - Introduction to Digital Design - November 2, 2000 Since the excitation function of a D ip- op is D(t) = Q(t + 1) is, the D input for each ip- op implementation corresponds to its characteristic function. That for a SR ip- op for a T ip- op for a JK ip- op D(t) = Q(t + 1) = S + R Q(t) 0 D(t) = Q(t + 1) = T Q(t) D(t) = Q(t + 1) = Q(t)K + Q(t) J 0 0 The corresponding networks are shown in Figures 8.26. S Q D Q R CK Q’ Q’ (a) T D Q Q CK Q’ Q’ (b) J D K CK Q’ Q Q Q’ (c) Figure 8.26: Networks of Exercise 8.22 Solutions Manual - Introduction to Digital Design - November 2, 2000 Exercise 8.28 163 A modulo-7 up/down counter requires seven states. Since the counter is binary, the state assignment is speci ed. The system has two inputs: x the variable to be counted, and c, to control up (c = 1) or down (c = 0) counting. The state table is Input PS x = 0 x = 1(down) x = 1(up) 000 000 110 001 001 001 000 010 001 011 010 010 011 011 010 100 011 101 100 100 100 110 101 101 110 110 101 000 NS = z (a) Based on the excitation function for a T ip- op we obtain the following table for ip- op inputs: PS Input Q2Q1Q0 x = 0 x = 1(down) x = 1(up) 000 000 110 001 001 000 001 011 000 011 001 010 000 001 111 011 100 000 111 001 000 001 011 101 000 011 110 110 From K-maps we obtain: T2T1T0 0 0 0 T2 = x(cQ1Q0 + cQ2Q1 + c Q1Q0) T1 = x(cQ0 + Q2Q1 + c Q0) = x((c Q0) + Q2Q1) T0 = x(c + Q2 + Q1 + Q0)(c + Q2 + Q1) 0 0 0 0 0 0 The network is shown in Figure 8.33. (b) using D-type ip- ops the next state is given as input, Q(t + 1) = D(t), so the rst table shown in this exercise is used. This time, the next state bits for the case x = 0 have values di erent than zero, and for this reason we need to consider the cases x = 0 and x = 1 separately. Let the inputs of the D-type FFs be D2; D1, and D0. For the case x = 1, using K-maps, we obtain: D2(x = 1) = Q2Q0 + Q1Q0c + Q2Q1c + Q2Q1c + Q2Q1Q0c D1(x = 1) = Q1Q0c + Q1Q0c + Q1Q0c + Q2Q1Q0c D0(x = 1) = Q2Q1Q0 + Q2Q0c + Q1Q0c For x = 0 the expressions for Di are: D2(x = 0) = Q2 D1(x = 0) = Q1 D0(x = 0) = Q0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 Solutions Manual - Introduction to Digital Design - November 2, 2000 Combining both cases we obtain the expressions: D2 = (Q2Q0 + Q1Q0c + Q2Q1c + Q2Q1c + Q2Q1Q0c )x + Q2x D1 = (Q1Q0c + Q1Q0c + Q1Q0c + Q2Q1Q0c)x + Q1x D0 = (Q2Q1Q0 + Q2Q0c + Q1Q0c )x + Q0x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The network is shown in Figure 8.33. (c) the implementation of this circuit using a combination of T and D-type ip- ops is a combination of the cases presented in the previous two designs. Considering the two least signi cant state bits stored in T-type FFs and the most-signi cant in a D-type FF, the switching expressions are: D2 = (Q2Q0 + Q1Q0c + Q2Q1c + Q2Q1c + Q2Q1Q0c )x + Q2x T1 = x((c Q0) + Q2Q1) T0 = x(c + Q2 + Q1 + Q0)(c + Q2 + Q1) 0 0 0 0 0 0 0 0 0 0 0 The network for this case is easily obtained from the other networks given for parts (a) and (b). Solutions Manual - Introduction to Digital Design - November 2, 2000 c Q1 Q x c Q2 Q x c’ Q1’ Q0’ x 165 T2 T CK Q Q2 c Q0’ x Q1 Q2 x T1 T CK Q Q1 c Q2 Q1 Q0 c Q2 Q1 Q0 x T0 CK Q0 T Q (a) T-type FF implementation Q1’ Q0’ c’ Q1’ Q0 c Q1 Q0 c’ Q2’ Q1 Q0’ c x x’ Q1 D1 D CK Q Q1 Q2 Q0 Q1 Q0 c Q2 Q1’ c Q2 Q1 c’ Q2’ Q1’ Q0’ c’ x x’ Q2 Q2 Q1’ Q0’ Q2’ Q0’ c Q1 Q0’ c’ D2 D CK Q Q2 x x’ Q0 D0 D CK Q Q0 (b) D-type FF implementation Figure 8.33: Networks for Exercise 8.28 ...
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