Unformatted text preview: 41 Chapter 4
Exercise 4.1 a gure 4.17a presents a valid gate network b the network in gure 4.17b is not valid since: the load factor L imposed to one of the 2input AND gates exceeds the fanout factor F of this gate; two outputs are connected together. c gure 4.17c presents a valid network. There's no active loop in the network because variable b interrupts the loop in two di erent points. When b = 0, the analysis of the network gives: z1 = ad 4.1 z0 = ad + c 4.2 When b = 1, the output switching expressions are: z 1 = z0 d 4.3 z0 = e + c 4.4 As we can see from the equations, there is no feedback of signals in the physical loop, and the network is combinational.
Exercise 4.2 Exercise 4.3 Gate Type Inputs Output A AND2 A1 A3 B Gates: C D E AND2 AND2 OR2 NOT A2 B1 B2 C1 C2 D1 D2 E1 B3 C3 D3 E2 FROM X Y W Z Connections: TO A3 A3 B3 B3 C3 D3 E2 A1 A2 B1 B2 D1 C1 D2 E1 C2
T R Exercise 4.4 The network is shown in gure 4.1. It's a valid network. Exercise 4.5 The network for this exercise is presented in Figure 4.2. 42 Solutions Manual  Introduction to Digital Design  January 26, 1999 R A S
B T X Y C E D Z Figure 4.1: Network for Exercise 4.4
R S Z E C A B T D Figure 4.2: Network for Exercise 4.5 It is an invalid network since the outputs of gates D and E are connected to the same point. As we don't know the function implemented by the net, any modi cation can be done to remove this connection. One possible solution is given in the table that follows: From To R A1 S A2 A B1 B C1 E C2 T D1 A2 D1
D C E1 E2 B2
Z In gure 4.17, networks a and c are loopfree. Network b has a loop in one of the OR gates. In gure 4.20, network a has a loop and network b is loopfree. : The operation speci ed by gx; y; z = x0yz + xy0 + y0z is universal because gx; 1; 1 = x0 realizes the NOT operation, and gx; 0; z = x + z realizes the OR operation. Since the set fOR; NOT g is universal, the g operation is also universal.
Exercise 4.7 Exercise 4.6 Solutions Manual  Introduction to Digital Design  January 26, 1999 43 To show that the set fXNOR; ORg is universal it su ces to show a realization of the NOT operation. The XNOR operation is de ned as Exercise 4.8 : XNORx; y = xy + x0 y0
Assuming that the constant 0 is available, we have: NOT x = XNORx; 0 = x:0 + x0 :1 = x0
The function * is: x y = x0 y. Observe that this function is not commutative x y 6= y x. For this reason, the order of inputs must be observed. The NOT gate is obtained as
Exercise 4.9 x0 = x0 1 = x 1
The AND gate is mapped to the * function as: x y = x0 0 y = x0 y = x 1 y
The networks to obtain the NOT and AND gates from the *" gate are shown in Figure 4.3. Since the * gate can implement the set fNOT,ANDg, and the set fNOT,ANDg is universal, the * gate is also universal.
x 1 * NOT gate x’ x 1 * y AND gate * xy Figure 4.3: Implementing a NOT and AND gates using the * gate
Exercise 4.10 Using backward analysis, and the node names presented in gure 4.4.
x1 T2 z1 x0 T1 T3 z0 T4 Figure 4.4: NANDNOR network for Exercise 4.9 44 Solutions Manual  Introduction to Digital Design  January 26, 1999 z1 = T2 T3 0 = x1 T1 0 T1 x0 0 0 = x1 T1 + T1 x0 = T1 x1 + x0 = x1 x0 0 x1 + x0 = x01 + x00 x1 + x0 = x01 x0 + x1 x00 = x1 x0 z0 = T3 + T4 0 = x0 T1 0 + T1 + x0 0 0 = x00 + T10 + T10 x00 0 = x00 + T10 0 = x0 T1 = x0 x1 x0 0 = x0 x01 + x00 = x0 x01 Mixed logic notation could be used in this problem and the network could be transformed in the one showed in gure 4.5. The equation obtained by backward analysis are now:
x1 T2 z1 x0 T1 T3 z0 T4 Figure 4.5: Mixed Logic Notation  Exercise 4.9 z1 = T2 + T3 = x1 T1 + T1 x0 = T1 x1 + x0 = x01 + x00 x1 + x0 = x01 x0 + x1 x00 = x1 x0 z0 = T3 T4 = x0 T1 T1 + x0 = x0 T1 = x0 x01 + x00 = x0 x01 The analysis turns out to be less complex.
Exercise 4.11 We obtain the following expressions: z = x01 + x2 x1 + x1 x0 x2 x1 + x2 x0 + x02 x2 x0 + x1 x0 + x00 0 = x01 + x2 + x0 x02 + x1 + x0 x00 + x1 + x2 0 = x01 + x2 + x0 0 + x02 + x1 + x0 0 + x00 + x1 + x2 0 = x1 x02 x00 + x2 x01 x00 + x0 x01 x02
that is, the output is 1 whenever exactly two of the inputs are 0. Solutions Manual  Introduction to Digital Design  January 26, 1999 45 Exercise 4.12 We have: z3 z2 z1 z0 = = = = x00 x03 + x02 x1 + x0 x01 + x00 x3 + x0 x02 + x1 x2 + x01 + x00 x3 x2 + x0 x2 + x1 These switching functions are shown in the next table: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i x3 x2 x1 x0 z3 z2 z1 z0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Looking at the input values in the range 3 to 12 that correspond to the decimal values 0 to 9 in excess3 code, and reordering the output bits zi we obtain: xEx,3 x3 x2 x1 x0 z0 z1 z2 z3 zBCD
0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 The second table shows that the network implements an Excess3 to BCD decoder. 46
Exercise 4.13 Solutions Manual  Introduction to Digital Design  January 26, 1999 aThe switching expressions are: Eout G z0 z1 z2 = = = = = 00000000 EinI0 I1 I2 I3 I4 I5I6 I7 0 EinEout 0 000 000 EinI7 + I6 I5 + I6 I5 I4 I3 + I6 I4I2 I1 000 00 EinI7 + I6 + I6 I5 I4 I3 + I5 I4 I2 0 EinI7 + I6 + I6 I5 + I4 bSince a highlevel description is not obvious from these expressions, we evaluate and present the following table: Ein I7 I6 I5 I4 I3 I2 I1 I0 Eout G z2 z1 z0
0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 To get a highlevel description we assume that the bitvector z is the radix2 representation of the integer z . From the table we obtain: j = 0 for k z = 0 if Ij = 1 and Ik otherwise j and Ein = 1 and Ij = Eout = 1 if Ein = 1otherwise 0 for all j 0 G = 1 if Ein = 1 and Ij = 1 for some j 0 otherwise
In words, let us call Ein the module network enable. Then: 4.5 4.6 4.7 Eout is 1 when the module is enabled and all Ii inputs are 0. G is 1 if the module is enabled and at least one of the Ii inputs is 1. z corresponds to the highest index of the inputs Ii with value 1.
Such a network is called a priority encoder studied in Chapter 9. c The load factor of each input is calculated considering that each AND or NOT gate has an input factor of 1. Solutions Manual  Introduction to Digital Design  January 26, 1999 47 Input Load Factor 0 Ein 1 0 I7 2 0 I6 2 0 I5 2 0 I4 2 0 2 I3 0 I2 2 0 I1 2 0 I0 1 The maximum delay for the network is obtained considering number and type of gates of each 0 path from inputs to the outputs. The critical path in this case is the one that goes from input I6 0 to output z0 . 00 TpLH I6 ; z0 = tpLH NOT + tpHLNOT + tpHL AND5 + tpHL OR4 + tpLH NOT
00 TpLH I6 ; z0 = 0:02 + 0:038 2 + 0:05 + 0:017 3 + T1 + 0:45 + 0:025 1 + 0:02 + 0:038 L 00 TpLH I6 ; z0 = 0:692 + T1 + 0:038 L 00 TpHL I6 ; z0 = tpHLNOT + tpLH NOT + tpLH AND5 + tpLH OR4 + tpHL NOT 00 TpHL I6 ; z0 = 0:05 + 0:017 2 + 0:02 + 0:038 3 + T2 + 0:13 + 0:038 1 + 0:05 + 0:017 L 00 TpHL I6 ; z0 = 0:436 + T2 + 0:017 L where T1 and T2 are the HL and LH propagation delays for an AND gate with 5 inputs and load factor of 1, respectively. The values of T1 and T2 are obtained by decomposition of the AND5 gate into the gates listed in Table 3.1 of the book. This decomposition is: ANDx4 ; x3 ; x2 ; x1 ; x0 = ANDANDx4 ; x3 ; x2 ; ANDx1 ; x0 The resulting delays are: T1 = tpHLAND3 + tpHLAND2 = 0:18 + 0:018 + 0:16 + 0:017L = 0:358 + 0:017L = 0:392 T2 = tpLH AND3 + tpLH AND2 = 0:2 + 0:038 + 0:15 + 0:037L = 0:388 + 0:037L = 0:462 The delays of the critical path become: 00 TpHL I6 ; z0 = 0:436 + 0:462 + 0:017L = 0:90 + 0:017L
00 TpLH I6 ; z0 = 0:692 + 0:392 + 0:038L = 1:08 + 0:038L d Timing diagram, see gure 4.6: 48 Solutions Manual  Introduction to Digital Design  January 26, 1999 AND5 I6’ A B AND3 AND2 C OR4 z0 z0’ I6’ A 0.084 0.134 0.096 0.101 0.392 0.168 0.475 0.05+0.017L 0.02+0.038L B 0.462 C z z0’ Figure 4.6: Timing diagram of Exercise 4.13
Exercise 4.14 a The switching expression for output z is z = E I0 s02s01s00 + I1 s02s01 s0 + I2 s02 s1 s00 + I3 s02 s1 s0 + I4 s2 s01 s00 + I5s2 s01 s0 + I6 s2s1 s00 + I7s2 s1s0
or z=E 7 X
i=0 Ii mi s2 ; s1; s0 b A highlevel description is z = Is if E=1 0 otherwise
where s = 4s2 + 2s1 + s0 . This function corresponds to an 8input multiplexer selector, that is discussed in Chapter 9 of the textbook. c The load factor of each input is 1, since each input is connected to only one gate input in the circuit. The load applied to each gate is: gate Load NOT connected to E 0 8 NOT gates connected to si 5 NOT gates to restore si 4 AND gates 1 OR gate L1 + 1 NOT used to generate z 0 L2 where, L1 and L2 are the Load imposed to the outputs z and z 0 respectively. Solutions Manual  Introduction to Digital Design  January 26, 1999 49 The delay of this network cannot be calculated based on the table given because there are no expressions for an AND gate with 5 inputs and an OR gate with 8 inputs. Calling these delays: tpLH AND5 tpHLAND5 tpLH OR8 tpHL OR8 = = = = T1 T2 T3 T4 the critical path delay is: tpLH s2 ; z0 = tpLH NOT + tpHLNOT + tpHL AND5 + tpHLOR8 + tpLH NOT = 0:02 + 0:038 5 + 0:05 + 0:017 4 + T2 + T4 + 0:02 + 0:038 L2 = 0:35 + T2 + T4 + 0:038 L2 0 = tpHL NOT + tpLH NOT + tpLH AND5 + tpLH OR8 + tpHL NOT tpHLs2 ; z = 0:05 + 0:017 5 + 0:02 + 0:038 4 + T1 + T3 + 0:05 + 0:017 L2 = 0:36 + T1 + T3 + 0:017 L2
The values of T1 ; T2 ; T3 and T4 are obtained by decomposition of the AND5 and OR8 gates into the gates listed in Table 3.1 of the book. This decomposition is: ANDx4 ; x3 ; x2 ; x1 ; x0 = ANDANDx4 ; x3 ; x2 ; ANDx1 ; x0
and ORx7 ; x6 ; : : : ; x1 ; x0 = ORORx7 ; x6 ; x5 ; x4 ; ORx3 ; x2 ; x1 ; x0
The resulting delays are: T1 T2 T3 T4 = = = = tpLH AND3 + tpLH AND2 = 0:2 + 0:038 + 0:15 + 0:037 = 0:43 tpHLAND3 + tpHLAND2 = 0:18 + 0:018 + 0:16 + 0:017 = 0:38 tpLH OR4 + tpLH OR2 = 0:13 + 0:038 + 0:12 + 0:037L1 + 1 = 0:33 + 0:037L1 tpHLOR4 + tpHLOR2 = 0:45 + 0:025 + 0:2 + 0:019L1 + 1 = 0:69 + 0:019L1 d timing diagram presented in gure 4.7. We de ne the modules as indicated in gure 4.8. For module M1 we obtain the switching expression:
Exercise 4.15 y = abc + ab0 c0 + a0 bc0 + a0 b0c0
A highlevel description is: y= 1 if there are 0 or 2 inputs with value 1 0 otherwise 4.8 Module M1 implements a 3input evenparity function which we denote EP a; b; c. 50 Solutions Manual  Introduction to Digital Design  January 26, 1999 AND5 s2 A B AND3 AND2 C OR4 OR8 OR2 z z’ s2 A 0.14 0.17 0.21 0.12 0.38 0.33+0.037L1 0.69+0.019L1 0.02+0.038L2 B 0.43 C z z’ 0.05+0.017L2 Figure 4.7: Timing diagram of Exercise 4.14 Module M2 has three inputs e, f and g, and two outputs z1 and z0 . The switching expressions are: z1 = efg + ef 0g0 + e0fg0 + e0 f 0 g0 z0 = e0 f 0g0 + e0fg + ef 0 g + efg0 0
The rst expression corresponds to the evenparity function EP e; f; g and the second one to the oddparity function OP e; f; g. By substitution we obtain: z1 = EP EP I8 ; I7 ; I6 ; EP I5 ; I4 ; I3 ; EP I2 ; I1 ; I0 = OP I8 ; I7 ; :::; I0
since an even number of groups among 3 groups with an even number of 1 inputs correspond to an odd number of 1 inputs overall. z0 = OP EP I8 ; I7 ; I6 ; EP I5 ; I4 ; I3 ; EP I2 ; I1 ; I0 = EP I8 ; I7 ; :::; I0
since an odd number of groups among 3 groups with an even number of 1 inputs correspond to an even number of 1 inputs overall. That is, the network implements the evenparity and oddparity functions of nine inputs. Delay of the network is obtained by the following expression for the path from input I2 to output z1 : TpLH I2 , z1 = tpLH NOT + tpHLOR4 + tpHLAND3 + tpHLNOT + tpLH NOT + tpHLOR4 + tpHLAND3 + tpHLNOT + tpLH NOT = 0:02 + 0:038L + 0:45 + 0:025 1 + 0:18 + 0:018 1 + 0:05 + 0:017 4 + 0:02 + 0:038 5 + 0:45 + 0:025 1 + 0:18 + 0:018 1 + 0:05 + 0:017 2 + 0:02 + 0:038 3 = 1:91 + 0:038L Solutions Manual  Introduction to Digital Design  January 26, 1999 51 I8 I7 I6 I5 I4 I3 I2 I1 I0 a b M1 y c a b M1 y c a b M1 y c e f M2 g z1 z0 Figure 4.8: Modules used in Exercise 4.15 TpHLI2 , z1 = tpHLNOT + tpLH OR4 + tpLH AND3 + tpLH NOT + tpHLNOT + tpLH OR4 + tpLH AND3 + tpLH NOT + tpHL NOT = 0:05 + 0:017L + 0:13 + 0:038 1 + 0:2 + 0:038 1 + 0:02 + 0:038 4 + 0:05 + 0:017 5 + 0:13 + 0:038 1 + 0:2 + 0:038 1 + 0:02 + 0:038 2 + 0:05 + 0:017 3 = 1:37 + 0:017L
We partition the network as shown in Figure 4.9. Module M0 has two inputs a and b, and three outputs x, y and z . In particular, as marked in the gure, the output x of each module M0 is used as an input to a module M5 . The expressions for the outputs of module M0 which has inputs Ai and Bi are:
Exercise 4.16 xi = Ai + Bi zi = Ai + BiA0i + Bi0 = Ai Bi yi = Ai + Bi 0 = A0i Bi0 zi = Ai Bi0 = A0i + Bi0
Module M1 implements the expression:
00 0 00 c1 = c00 z0 + y0 0 = c0 + z0 y0 = c0 y0 + z0y0 = c0 A0 + B0 + A0 B0 because zi0 yi0 = Ai Bi Ai + Bi = Ai Bi = zi0 . 52
C
0 Solutions Manual  Introduction to Digital Design  January 26, 1999 A 0 B M0 0 A 1 B M0 1 A 2 B M0 2 A 3 B M0 3 y z x x0 x1 x2 x3 c0 M1 c1 M5 S S M5 M2 c2 M5 S M3 c3 M5 S M4 0 1 2 3 C 4 Figure 4.9: Modules used in Exercise 4.16 The same way we obtain the expressions for M2 , M3 and M4 as: c2 = c00 z0 z1 + y0 z1 + y10 0 0 = c00 z0 + y0 z1 + y1 0 = c01 z1 + y1 0 = c1 y1 + z1 = c1 A1 + B1 + A1 B1 0 z0 z1 z2 + y0 z1 z2 + y1 z2 + y2 0 c3 = c0 0 0 = c0 z0 z1 + y0 z1 + y1 z2 + y2 0 = c02 z2 + y2 0 = c2 y2 + z2 = c2 A2 + B2 + A2 B2 0 z0 z1 z2 z3 + y0 z1 z2 z3 + y1 z2 z3 + y2 z3 + y3 0 c4 = c0 = c0 z0 z1 z2 + y0 z1 z2 + y1 z2 + y2 z3 + y3 0 = c03 z3 + y3 0 = c3 A3 + B3 + A3 B3 From these previous expressions we obtain a general form: ci+1 = Ai + Bici + Ai Bi Module M5 implements the expression: Si = ci xi = ci Ai Bi To prove that the circuit implements a 4bit adder we will show that it works for 2bit addition, and claim that the circuit works for 4 bits, based on the regularity of the circuit implementation. Perfect induction over all the possible inputs is practically impossible, given the large number of input combinations. From the previous equations, we are able to build the following switching function table for the internal variables c2 ; c1 ; p1 ; and p0 : Solutions Manual  Introduction to Digital Design  January 26, 1999 53 c0 B1B0
000 001 010 011 100 101 110 111 00 0000 0001 0010 0011 0000 0101 0010 1111 01 0001 0100 0011 1110 0101 0100 1111 1110 A1 A0 c2 c1 p1p0 10 0010 0011 1000 1001 0010 1111 1000 1101 11 0011 1110 1001 1100 1111 1110 1101 1100 Since Ai = Bi = 0 for i 1, that implies p2 = p3 = 0 and c3 = c4 = 0. With these conditions, the above table, and knowing that Si = pi ci we have: S3 = 0 S2 = c2 S1 = p1 c1 S0 = p0 c0 and the following table results to show the relation of inputs and outputs of the given circuit: c0 B1B0
000 001 010 011 100 101 110 111 00 000 001 010 011 001 010 011 100 01 001 010 011 100 010 011 100 101 A1 A0 c2 S1 S0 10 010 011 100 101 011 100 101 110 11 011 100 101 110 100 101 110 111 Observe that the table describes the function of a 2bit adder, with a carryin bit c0 . From this result, taking into account the regularity of the design, we claim that the design implements a 4bit adder. ...
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 Winter '09
 Ercegovac,M.D.
 Konrad Zuse

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