CSM51Asolution_chapter5

CSM51Asolution_chapter5 - 55 Chapter 5 Exercise 5.1 z x...

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Unformatted text preview: 55 Chapter 5 Exercise 5.1 z x 0101 0100 y x z -011 -001 y f1 Exercise 5.2 f0 a the K-map for E x; y; z  = P m1; 5; 7 is: z x 0100 0110 y 0 bE w; x; y; z  = w x y + y z + xz 0 0 0 z 0 1 1 0 1 1 1 1 1 0 0 0 y Exercise 5.3 w 1 1 1 0 x a E w; x; y; z  = M 1; 3; 4; 7; 10; 13; 14; 15 = z 1 0 1 1 0 1 0 1 0 0 0 1 y bE w; x; y; z  = Q P m0; 2; 5; 6; 8; 9; 11; 12 1 1 0 0 w x P m0; 4; 5; 9; 11; 14; 15; dcw; x; y; z = P m2; 8 56 Solutions Manual - Introduction to Digital Design - January 26, 1999 z 1 1 0 0 1 0 1 0 0 1 1 y 0 1 0 x w c E x; y; z  = P m0; 1; 4; 6 = Q M 2; 3; 5; 7 z x 1100 1001 y Exercise 5.4 a Kmap and prime implicants f w; x; y; z = P m0; 1; 2; 3; 5; 7; 8; 10; 11; 15 z 1 0 0 1 0 0 w 1 1 0 0  1 1 10 x 10 1 1 y prime implicants: w x ; w z; x y; yz; x z b essential prime implicants: w z; yz; x z cThe minimal sum of products for this function is unique: f w; x; y; z = w z + yz + x z 0 0 0 0 0 0 0 0 0 0 Exercise 5.5 a More implicants than minterms x 0 0 0 0 z  0 1 10 0000 y implicants: x yz; x y z , and x z minterms: x yz and x y z b Equal number of implicants and minterms 0 0 0 Solutions Manual - Introduction to Digital Design - January 26, 1999 57 x  1 0 0 0 0000 y z implicant: x y z minterm: x y z 0 0 0 0 0 0 Exercise 5.6 a E w; x; y; z  = M 1; 3; 4; 7; 10; 13; 14; 15 = z Q P m0; 2; 5; 6; 8; 9; 11; 12 w   1 0 0 1  0 1 1 0 x 1000  1 1 1 0 y minimal sum of products: wy z + wx z + w x z + w yz + w xy z 0 0 0 0 0 0 0 0 0 0 x 10  0 1 10 11 z  0 1  01  w 0 0 1 0 y minimal product of sums: w + x + z w + y + z x + y + z w + x + z w + x + y + z  0 0 0 0 0 0 0 0 0 0 58 bE w; x; y; z  = Solutions Manual - Introduction to Digital Design - January 26, 1999 P m0; 4; 5; 9; 11; 14; 15; dcw; x; y; z = P m2; 8 z  100 1 0 10 x 0 0 1 1  - 1 1 0 y z w minimal SP: w y z + w y x + wx z + wxy 0 0 0 0 0 0 w 1 1 0 -  0 0 - 100  x 0 1 1  110 y minimal PS: w+x+z'w+y'x+y'+zw'+x'+y P Q c E x; y; z  = m0; 1; 4; 6 = M 2; 3; 5; 7 z  1 1 0 0 x 1 0 1 0 y minimal sum of products: x y + xz 0 0 0 x 0 0  1 1 0 0  1 0 0 1 y 0 z minimal product of sums: x + y x + z  Solutions Manual - Introduction to Digital Design - January 26, 1999 59 Exercise 5.7 f w; x; y; z  = one set1; 5; 7; 8; 9; 10; 14 w  0 1  0 0  0110 x  0 1 00   1 1 0 1 y 0 0 0 0 0 0 0 0 0 z a prime implicates are: w + z ; w + x + y ; x + y + z ; w + y + z ; w + x + z ; w + x + y; x + y + z  b essential prime implicate is: w + z  c a minimal product of sums expression that implements f w; x; y; z  is: 0 0 0 E w; x; y; z = w + z x + y + z w + x + z x + y + z 0 0 0 0 0 0 the solution is not unique because there are other ways to cover the 0-cells not covered by the essential prime implicate with the same number of terms. Exercise 5.8 Input: a; b; c; d, with a; b; c; d 2 f0; 1g Output: y 2 f0; 1g Function: y = 1 if 8a + 4b + 2c + d is prime 0 otherwise input value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 y 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0  60 Solutions Manual - Introduction to Digital Design - January 26, 1999 a 0 0 0 0  0  1 1  1  10 b 1 0 0  0 01 c 0 0 0 0 0 0 0 0 0 d From the Kmap we get the following prime implicants: a bd; b cd; a b c; a cd, and bc d The essential prime implicants are: b cd; a b c, and bc d A minimal sum of products for function y is: 0 y = b cd + a b c + bc d + a cd 0 0 0 0 0 and the gate network that implements this expression is shown in Figure 5.1. b’ c d a’ b’ c b c’ d a’ c d y Figure 5.1: AND-OR gate network for prime detector" Exercise 5.8 a  00 01 01 0 0 d 1 1 0 1 c 0 0 0 1 0 b 0 0 From the Kmap we get the following prime implicates: b + d; a + d; b + c; c + d and a + b + c . Only the c + d prime implicate is not essential. So, the minimal product of sums in this case is: y = b + da + db + ca + b + c  and the gate network that implements this expression is shown in Figure 5.2. Notice that the cost of the product of sums is lower. 0 0 0 0 0 0 0 Solutions Manual - Introduction to Digital Design - January 26, 1999 61 b’ d a’ d b c a’ b’ c’ y Figure 5.2: OR-AND gate network for prime detector" Exercise 5.8 To repeat the Exercise 5.8 using the Quine-McCluskey minimization method we make use of two tables. The rst table is used to obtain the prime implicants and the second to select the minimum cover. The one set for this function is one set= f2; 3; 5; 7; 11; 13g Minterms 3-literal Prods 2-literal Prods 1-literal Prods 0010 N 0010011 N 0101 N -101 -011 0-11 01-1 Exercise 5.9 0111 N 1011 N 1101 N The second table consider the prime-implicants obtained in the previous table: Prime Implicants 2 3 5 7 11 13 Essential 001xx -101 x x -011 x x 0-11 x x 01-1 xx Based on the table, the function is represented by 3 essential terms and the minterm 7 must be covered with either 0 , 11 or 01 , 1. The minimal SP expressions are: y = a b c + bc d + b cd + a cd 0 0 0 0 0 or y = a b c + bc d + b cd + a bd 0 0 0 0 0 62 Exercise 5.10 Solutions Manual - Introduction to Digital Design - January 26, 1999 A high-level description for this system is: Input: a; b; c; d; e 2 f0; 1g Output: f 2 f0; 1g Function:  f = 1 if a + b + c + d + e  3 0 otherwise Using Quine-McCluskey minimization method we obtain the following table: Minterms 4-literal products 3-literal products 00111 N 0-111 N - -111 01011 N -0111 N -1-11 10011 N 01-11 N 1- -11 01101 N 10-11 N -11-1 10101 N 1-011 N 1-1-1 11001 N 011-1 N 11- -1 01110 N -1101 N -11110110 N 101-1 N 1-1111010 N 1-101 N 11-111100 N 110-1 N 111- 11-01 N 01111 N 0111- N 10111 N -1110 N 11011 N 1011- N 11101 N 1-110 N 11110 N 1101- N 11-10 N 11111 N 1110- N 111-0 N -1111 N 1-111 N 11-11 N 111-1 N 1111- N To obtain a cover for the minterms we use a second table to identify the essential prime implicants, as shown below: 7 11 13 14 15 19 21 22 23 25 26 27 28 29 30 31 Essential Prime - -111 x x x x -1-11 x x x x 1- -11 x x x x -11-1 x x x x 1-1-1 x x x x 11- -1 x x x x -111xx xx 1-11xx xx 11-1xx xx 111- xxxx is: All the terms obtained in the rst table are essential prime implicants. The minimal expression f = abc + abd + abe + acd + ace + ade + bcd + bce + bde + cde Solutions Manual - Introduction to Digital Design - January 26, 1999 63 and the corresponding two-level gate network is shown in Figure 5.3 on page 63. Note that the OR gate has 10 inputs, which might make a two-level implementation impractical. a b d a b c b c d a c d c d e b c e b d e a b e a d e a c e f Figure 5.3: Majority function - Exercise 5.10 A high-level speci cation for the error detector is: Input: x is a 2-out-of-5 code represented as x = a; b; c; d; e, where a; b; c; d; e 2 f0; 1g. Output: f 2 f0; 1g. Function:  f = 0 if the number of 1s in the input is 2 1 otherwise The synthesis of this function using Quine-McCluskey minimization method is shown in Table 5.1. The obtained 3-literal products generate a Prime-implicant chart similar to the one shown in Exercise 5.10, where it was concluded that all products are essential. The minimal sum of products is: Exercise 5.11 f = a b c d + abc + abd + acd + bcd + abe + ace + ade + bce + bde + cde +a b c e + a b d e + a c d e + b c d e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The gate network that implements the function f is shown in Figure 5.4. Note that the OR gate has 15 inputs, which might make a two-level implementation impractical. 64 Solutions Manual - Introduction to Digital Design - January 26, 1999 Minterms 4-literal prods 3-literal prods 00000 N 0000- -111 000-0 -1-11 00001 N 00-00 -11-1 00010 N 0-000 -11100100 N -0000 1- -11 01000 N 1-1-1 10000 N 0-111 N 1-11-0111 N 11- -1 00111 N 01-11 N 11-101011 N -1011 N 111- 01101 N 011-1 N 01110 N -1101 N 10011 N 0111- N 10101 N -1110 N 10110 N 1-011 N 11001 N 10-11 N 11010 N 1-101 N 11100 N 101-1 N 1-110 N 01111 N 1011- N 10111 N 11-01 N 11011 N 110-1 N 11101 N 11-10 N 11110 N 1101- N 111-0 N 11111 N 1110- N 1111- N 111-1 N 11-11 N 1-111 N -1111 N Table 5.1: Quine-McCluskey table for Exercise 5.11 Solutions Manual - Introduction to Digital Design - January 26, 1999 65 a b d a b c b c d a c d a c e a b e b c e a d e f b d e c d e a’ b’ c’ a’ e’ b’ d’ e’ b’ c’ d’ e’ a’ c’ d’ e’ a’ b’ c’ d’ Figure 5.4: Network for Exercise 5.11 Exercise 5.12 A high-level speci cation for this exercise is: Input: a; b 2 f0; 1; 2; 3g and c 2 f0; 1g. Output: z 2 f0; 1; 2; 3; 4; 5; 6; 7g Function: z = a + b + c The input is represented by 2-bit vectors a1 ; a0  and b1 ; b0 , and the output is represented by a 3-bit vector z = z2 ; z1 ; z0 . Using Quine-McCluskey tabular method we obtain the following tables, based on the switching function table presented in Exercise 2.46. The synthesis for z0 is shown in Table 5.2, z1 is shown in Table 5.3, and z2 is shown in Table 5.4. in in 66 Solutions Manual - Introduction to Digital Design - January 26, 1999 Minterms 4-literal prods 3-literal prods 00001 N 000-1 N 0-0-1 00100 N 0-001 N 0-1-0 10000 N 001-0 N 1-0-0 0-100 N 00011 N 100-0 N 1-1-1 00110 N 1-000 N 01001 N 01100 N 0-011 N 10010 N 0-110 N z0 11000 N 010-1 N 011-0 N 01011 N 1-010 N 01110 N 110-0 N 10101 N 11010 N 101-1 N 1-101 N 10111 N 11101 N 1-111 N 111-1 N 11111 N 1 3 4 6 9 11 12 14 16 18 21 23 24 26 29 31 Essential Prime 0-0-1 x x xx 0-1-0 xx xx 1-0-0 xx xx 1-1-1 xx xx Table 5.2: Exercise 5.12 - synthesis of z0 output Solutions Manual - Introduction to Digital Design - January 26, 1999 67 Minterms 4-literal prods 3-literal prods 00010 N 000101000 N 00-10 00011 N 00101 N 00110 N 01001 N 01100 N 10001 N 10010 N 10100 N 11000 N 10101 N 01111 N 11011 N 11110 N -0010 010001-00 -1000 -0101 10-01 1010-1111 11-11 1111- z1 11111 N 2 3 5 6 8 9 12 15 17 18 20 21 24 27 30 31 Essential Prime 0001- x x 00-10 x x -0010 x x 0100xx 01-00 x x -1000 x x -0101 x x 10-01 x x 1010xx -1111 x x 11-11 x x 1111xx Table 5.3: Exercise 5.12 - synthesis of z1 output 68 Solutions Manual - Introduction to Digital Design - January 26, 1999 z2 Minterms 4-literal prods 3-literal prods 2-literal prods 01010 N 0101- N 01-1- N -1-101-10 N -101- N 00111 N -1010 N -1-10 N 01011 N 01101 N 0-111 N - -111 01110 N -0111 N -1-11 N 10011 N 01-11 N -11-1 10110 N -1011 N -111- N 11001 N 011-1 N 1- -11 11010 N -1101 N 1-1111100 N 0111- N 11- -1 -1110 N 11-1- N 01111 N 10-11 N 111- 10111 N 1-011 N 11011 N 1011- N 11101 N 1-110 N 11110 N 110-1 N 11-01 N 11111 N 1101- N 11-10 N 1110- N 111-0 N -1111 N 1-111 N 11-11 N 111-1 N 1111- N 7 10 11 13 14 15 19 22 23 25 26 27 28 29 30 31 Essential Prime -1-1xx xx xx xx - -111 x x x x -11-1 x x x x 1- -11 x x x x 1-11xx xx 11- -1 x x x x 111- xxxx Table 5.4: Exercise 5.12 - synthesis of z2 output Solutions Manual - Introduction to Digital Design - January 26, 1999 69 The resulting expressions are: z0 = x0y0c + x0 y0c + x0 y0 c + x0 y0c z1 = x1x0 y1c + x1 y1y0c + x1x0 y1 y0 + x1 x0 y1 c + x1 y1 y0 c + x1 x0 y1 y0 + x1 x0 y1 c + x1 y1 y0 c + x1 x0 y1 y0 + x1 y1 y0 c + x1 x0 y1 c + x1 x0 y1 y0 z2 = x1y1 + x1 x0 y0 + x0 y1 y0 + y1 y0c + x0y1 c + x1 x0 c + x1 y0 c in 0 0 0 in 0 0 0 0 0 in 0 in 0 in in 0 0 in in 0 0 0 0 0 0 0 0 0 0 0 0 0 in in in 0 0 0 0 0 in in in in in The AND-OR networks are shown in Figure 5.5. They assume that the complement of inputs are also available. Because of the large number of inputs to the OR gates, a two-level implementation might not be practical. x0 y0 cin x0’ y0’ cin x0 y0’ cin’ x0’ y0 cin’ z0 x1 y1 x1 x0 y0 z2 x1’ x0 y1’ y0’ z1 total of 7 AND gates x1 y0 cin total of 12 AND gates x1 x0’ y1’ y0’ Figure 5.5: Network for Exercise 5.12 70 Exercise 5.13 Solutions Manual - Introduction to Digital Design - January 26, 1999 Input: x in the range 0; 15 Output: y in the range 0; 7 Function: y = x mod 7 The switching functions are shown in the table x = x3x2 x1x0  y = y2 y1y0  0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 000 001 010 011 100 101 110 000 001 010 011 100 101 110 000 001 From K-maps not shown we obtain the following minimal switching expressions y2 = x3 + x2 x2 + x1 + x0 x3 + x1 + x0x2 + x1  = x2 x1 + x3 x2 x1 x0 + x3 x2 x0 y1 = x3 + x1 x1 + x0 x3 + x2 + x0 x3 + x2 + x1 x3 + x1 + x0  = x3 x1 x0 + x3 x2 x1 + x3 x1 x0 + x2 x1 x0 y0 = x3 + x0 x3 + x2 + x0 x3 + x1 + x0x2 + x1 + x0 x3 + x2 + x1  = x3 x1 x0 + x3 x2 x0 + x3 x2 x1 x0 + x3 x1 x0 + x3 x2 x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Using the lowest cost version of the network that produces each output, we obtain the gate network shown in Figure 5.6. The multiplier is speci ed as follows: Inputs: x; y where x; y 2 f0; 1; 2; 3g Output: z 2 f0; 1; 2; 3; 4; 6; 9g Function: z = x  y Coding the inputs and outputs in a binary code, produces the switching function of the following table: Exercise 5.14 Solutions Manual - Introduction to Digital Design - January 26, 1999 71 x2 x1’ x3’ x2 x0’ x3 x2’ x1 x0 y2 x3 x0 x3’ x2 x0’ x3’ x1 x0’ y1 x2’ x1’ x0 x3 x2’ x1’ y0 x3 x1’ x0 x3’ x2’ x1 x3’ x1 x0’ x2’ x1 x0’ Figure 5.6: Exercise 5.13 x y z x1 x0 y1 y0 z3 z2 z1 z0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 From the table we get the following K-maps and expressions for the multiplier binary outputs: 72 Solutions Manual - Introduction to Digital Design - January 26, 1999 y0 0 0 0 0 0 0 0 0 0 0 0 1 0 0x 0 1  1 0 0 0 0 y0 000  0 1 1 x  0 1 0 1  1 10 0 0 0 0 0 1 1 0 y0 0 1 1 0 0 0x 0 0 0 x1 z2 x1 z1 0 0 x1 z0 y1 0 0 y1 y1 The NAND-NAND network is obtained directly from the sum of products. The correspoding network is presented in Figure 5.7. x0 y0 x1 x0’ y0 x0 y1 y0’ x1’ x0 y1 x1 y1’ y0 x1 x0’ y1 x1 y1 y0’ x1 x0 y1 y0 z0 z0 = x0y0 z1 = x1x0 y0 + x0 y1y0 + x1x0 y1 + x1 y1 y0 z2 = x1x0 y1 + x1 y1y0 Output z3 corresponds to only one minterm no Kmap is needed in this case: z3 = x1 x0 y1y0 0 0 z1 z2 z3 Figure 5.7: Network for a 2x2 bit multiplier. Exercise 5.14 Solutions Manual - Introduction to Digital Design - January 26, 1999 73 Input: binary code represented as b = b3 b2 b1 b0 , where b 2 f0; 1g Output: Gray code represented as g = g3 g2 g1 g0 , where g 2 f0; 1g Function: g is the Gray code that corresponds to b. The correspondence between binary and Gray codes is shown in the following table: i i Exercise 5.15 b3 b2 b1 b0 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 g3 g2 g1 g0 Gray 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 The correspoding Kmaps are as follows: g3 0 0 1 1 0 0 1 1 b0 0 0 1 1 0 0 b2 1 1 g2 0 1 0 1 0 1 0 1 b0 0 1 0 1 b3 b3  0 1 b2 0 1 b1 g1 0 1 1 0 0 1 1 0 b1 g0 b0 1 0 0 1 1 0 b2 0 1 b3 b3 b1  01 01 01 0 1 b0  01 01 b2 01 0 1 b1 74 Solutions Manual - Introduction to Digital Design - January 26, 1999 To obtain a NOR-NOR network we produce the minimal product of sums: g3 g2 g1 g0 = = = = b3 b2 + b3 b2 + b3  b1 + b2 b1 + b2  b0 + b1 b0 + b1  0 0 0 0 0 0 The gate network is presented in Figure 5.8. b0 b1 b0’ b1’ b1 b2 g1 b1’ b2’ b2 b3 b2’ b3’ b3 g3 g0 g2 Figure 5.8: Exercise 5.15 Using Quine-McCluskey minimization method to solve Exercise 5.15 we get Tables 5.5, 5.6, 5.7, and 5.8. Minterms are obtained from the switching function presented in Exercise 5.15. From the QM tables we obtain the expressions: Exercise 5.16 g3 g2 g1 g0 = = = = b3 b2 b3 + b2 b3 b1 b2 + b1 b2 b0 b1 + b0 b1 0 0 0 0 0 0 Solutions Manual - Introduction to Digital Design - January 26, 1999 75 g3 Minterms 3-literal prods 2-literal prods 1-literal prods 1000 N 100- N 1-0- N 1- - 10-0 N 10- - N 1001 N 1-00 N 1- -0 N 1010 N 1-0- N 1100 N 10-1 N 1-01 N 1- -1 N 1011 N 101- N 11- - N 1101 N 1-10 N 1-1- N 1110 N 110- N 11-0 N 1111 N 1-11 N 11-1 N 111- N Table 5.5: Exercise 5.16 - synthesis of g3 output Minterms 3-literal prods 2-literal prods 0100 N 010- N 01- 1000 N 01-0 N 10- 100- N 0101 N 10-0 N 0110 N 1001 N 01-1 N 1010 N 011- N 10-1 N 0111 N 101- N 1011 N g2 Table 5.6: Exercise 5.16 - synthesis of g2 output Minterms 3-literal prods 2-literal prods 0010 N 001- N -010100 N -010 N -10010- N 0011 N -100 N 0101 N 1010 N -011 N 1100 N 101- N -101 N 1011 N 110- N 1101 N g1 Table 5.7: Exercise 5.16 - synthesis of g1 output 76 Solutions Manual - Introduction to Digital Design - January 26, 1999 g0 Minterms 3-literal prods 2-literal prods 0001 N 0-01 N - -01 0010 N -001 N - -10 0-10 N 0101 N -010 N 0110 N 1001 N -101 N 1010 N -110 N 1-01 N 1101 N 1-10 N 1110 N Table 5.8: Exercise 5.16 - synthesis of g0 output A high-level speci cation of the system is: Input: x is an alphanumeric character coded in ASCII Output: z 2 f0; 1g Function:  z = 1 if x 2 fA; B; C; D; E g 0 otherwise Exercise 5.17 5:1 A 10000011 B 10000101 C 10000111 D 10001001 E 10001011 otherwise 0 Since all combinations producing output 1 have x6 x5 x4 x3 = 1000, we de ne m = x6 x5 x4 x3 . The K-map for this function is: 0 0 0 x6 x5 x4 x3 x2 x1 x0 z x0 x2 From the Kmap: 0mmm mm0 0 x1 A two-level NAND network is obtained from this expression. It has 3 6-input NAND gates and one 3-input NAND gate. The description of it is: NANDNANDx6 ; x5 ; x4 ; x3 ; x2 ; x1 ; NANDx6 ; x5 ; x4 ; x3 ; x2 ; x0 ; NANDx6 ; x5 ; x4 ; x3 ; x2 ; x1  For a NOR-NOR implementation we need to obtain an expression in PS form as follows: z = mx2 + x1 x2 + x1 + x0 = x6 x5 x4 x3 x2 + x1 x2 + x1 + x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 z = mx2 x1 + mx2 x0 + mx2 x1 0 0 0 Solutions Manual - Introduction to Digital Design - January 26, 1999 77 that corresponds to the following description: z = NORx6; x5 ; x4 ; x3 ; NORx2 ; x1 ; NORx2 ; x1 ; x0  0 0 0 The gate networks are easily obtained from these expressions and descriptions. A high-level speci cation for the system is: Input: x is a decimal digit, represented in BCD Output: y is an unsigned integer represented in binary Function: y = x2 The switching functions for this exercise are given as: Exercise 5.18 x BCD y = x2 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000000 0000001 0000100 0001001 0010000 0011001 0100100 0110001 1000000 1010001 Using K-maps we obtain: y0 y1 y2 y3 y4 y5 y6 = = = = = = = x0 0 x1 x0 x2 x1 x0 + x2x1 x0 x2 x1 + x2 x0 x2 x1 x3 0 0 0 0 The PLA implementation of this system is shown in gure 5.9. The high-level speci cation for this system is: Input: b is a decimal digit, represented in BCD Output: e is a decimal digit, represented in Excess-3 code Function: e = b The conversion of a BCD code, represented as b = b3 ; b2 ; b1 ; b0  to an Excess-3 code, represented by e = e3 ; e2 ; e1 ; e0 , is de ned by the following K-maps: Exercise 5.19 78 x3 x2 x1 Solutions Manual - Introduction to Digital Design - January 26, 1999 x0 OR Array 1 2 3 4 5 6 7 8 9 AND Array -- programmable connection -- connection made y6 y5 y4 y3 y2 y1 y0 Figure 5.9: PLA implementation for Exercise 5.18 b0 0 0 1 0 1 1 0 1 0 1 b -2 01  10 - 01 b0 1 0 1 0 b -2 - b3 e3 : b3 e2 : b1 b1 Solutions Manual - Introduction to Digital Design - January 26, 1999 79 b0 1 1 1 0 0 0 1 1 0 0 b -2 - b3 e1 : b3 e0 : b1 e3 e2 e1 e0 = = = =  10 10 -1 0 b0 0 0 - b1  1 1 b -2 - The minimal sum of products are: b1b2 + b0b2 + b3 b1b2 + b0b2 + b2b1 b0 b1b0 + b1b0 b0 0 0 0 0 0 0 0 The implementation of these expressions by a PLA is shown in gure 5.10. b3 b2 b1 b0 OR Array 1 2 3 4 5 6 7 8 9 AND Array -- programmable connection -- connection made e3 e2 e1 e0 Figure 5.10: PLA implementation of a BCD to Excess-3 converter A high-level speci cation for this system is: Input: x is a decimal digit, represented in Excess-3 code Output: y is a decimal digit, represented in 2-out-of-5 code Exercise 5.20 80 Solutions Manual - Introduction to Digital Design - January 26, 1999 Function: y = x The table that shows the correspondence between the excess-3 code x and the 2-out-of-5 code y is show in page 28 of the textbook Table 2.3. From the table we get the following K-maps: x0 0 1 0 0 0 1 0 1 0x 2 - 1 0 0 1 0 1 x0 x4 y0 : x4 y1 : x0  11 x 0 2 -00 x4 y2 : x0 0 1 0 x1 x1 -0 10 -1 0 x0   1x 2 - 0 x1 x4 y3 : 0 0 0 0 1 1 0 1  1x 2 - 0 x4 y4 : 1 0 0 1 0 0 1 0 x1 x1 0x 2 1 Using the K-maps we obtain the following minimal expressions for output y = y4 ; y3 ; y2 ; y1 ; y0 : y0 y1 y2 y3 y4 = = = = = x3 x2 + x2 x1 x2 x1 + x3 x1 x0 x1 x0 + x3 x2 + x2 x1 x0 x2 x0 + x2 x1 x0 x2 x0 + x3 x1 + x3 x1 x0 0 0 0 0 0 0 0 0 0 0 0 The implementation of these expressions using a PAL is shown in gure 5.11. A high-level speci cation for this system is: Input: x is a decimal digit represented in BCD Output: y = y1 y0 , where y1 and y0 are both BCD digits. Function: y = 3x. From this speci cation we de ne y = y7 ; y6 ; :::; y1 ; y0 , y 2 f0; 1g. The table for the switching functions is shown next: Exercise 5.21 i Solutions Manual - Introduction to Digital Design - January 26, 1999 81 0000 0000 0000 0001 0000 0011 0010 0000 0110 0011 0000 1001 0100 0001 0010 0101 0001 0101 0110 0001 1000 0111 0010 0001 1000 0010 0100 1001 0010 0111 The implementation of this function using a PAL is shown in Figure 5.12. Output y7 and y6 were not mapped to the PAL since they are always zero. No minimization was performed in this solution. An enable input was included to activate the circuit outputs. x = x3 x2x1 x0  y7 y6 y5 y4 y3y2 y1 y0 82 Solutions Manual - Introduction to Digital Design - January 26, 1999 I1 x0 0 0 4 8 12 16 20 24 28 O1 y0 I2 x1 8 IO2 y1 I3 x2 16 IO3 y2 I4 x3 24 IO4 y3 I5 Enable 32 IO5 y4 I6 40 IO6 I7 48 IO7 I8 56 O8 I9 I10 Figure 5.11: PAL implementation for Exercise 5.20 Solutions Manual - Introduction to Digital Design - January 26, 1999 83 I1 x0 0 0 4 8 12 16 20 24 28 O1 y0 I2 x1 8 IO2 y1 I3 x2 16 IO3 y2 I4 x3 24 IO4 y3 I5 enable 32 IO5 y4 I6 40 IO6 y5 I7 48 IO7 I8 56 O8 I9 I10 Figure 5.12: PAL implementation for Exercise 5.21 ...
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