CSM51Asolution_chapter6

# CSM51Asolution_chapter6 - 85 Chapter 6 Exercise 6.1 From...

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Unformatted text preview: 85 Chapter 6 Exercise 6.1 From Exercise 5.11, we know that the single-error detector for a 2-out-of-5 code a; b; c; d; e is implemented by the expression: E a; b; c; d; e = abc + abd + acd + bcd + abe + ace + ade + bce + bde + cde + a b c e + a b d e + acde +bcde Using only gates from Table 4.1 of the textbook we can generate all product terms but the OR operation of all 14 product terms must be implemented by a tree of gates. To minimize the delay in the implementation, we should use NAND gates. The generation of the product terms is done using 3 and 4-input NAND gates from Table 4.1. A 14-input NAND however is not available and should be obtained combining smaller gates. The large NAND gate may be decomposed into smaller ones as follows for a 4-input NAND to 2-input NANDs: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 abcd = ab + cd 0 0 0 The possibilities are: Network A - First Level: 1 NAND-6, 1 NAND-8, Second Level: 1 OR-2 0.40+0.037L 0.64+0.019L B - First Level: 1 NAND-4, 2 NAND-5, Second Level: 1 OR-3 0.37+0.038L 0.70+0.022L C - First Level: 2 NAND-3, 2 NAND-4, Second Level: 1 OR-4 0.27+0.038L 0.62+0.025L Even though the LH transition delay of network C is less than the one for network A, the HL transition delay of network C becomes worse when the output load is greater or equal to 3. For this reason we consider network A as the implementation of the 14-input NAND, since it is going to be less susceptible to output load values. The resulting circuit is presented in Figure 6.1, on page 86. The delay of the network is obtained from the critical paths NAND-4 ! NAND-6 ! OR-2 or NAND-3 ! NAND-8 ! OR-2: tpLH Delay tpHL TpLH net = maxtpHL NAND-4 + tpLH NAND-6 + tpLH OR-2; tpHLNAND-3 + tpLH NAND-8 + tpLH OR-2 = max0:12 + 0:051  1 + 0:24 + 0:037  1 + 0:12 + 0:037  L; 0:09 + 0:039 + 0:24 + 0:038 + 0:12 + 0:039L = max0:57 + 0:037L; 0:53 + 0:037L = 0:57 + 0:037L TpHL net = maxtpLH NAND-4 + tpHL NAND-6 + tpHL OR-2; tpLH NAND-3 + tpHL NAND-8 + tpHL OR-2 = max0:10 + 0:037  1 + 0:36 + 0:019  1 + 0:20 + 0:019  L; 0:07 + 0:038 + 0:42 + 0:019 + 0:2 + 0:019L = max0:72 + 0:019  L; 0:75 + 0:019L = 0:75 + 0:019L 86 Solutions Manual - Introduction to Digital Design - February 2, 1999 a b c a b d a c d b c d a b e a c e a d e b c e b d e c d e a’ b’ c’ e’ a’ b’ d’ e’ a’ c’ d’ e’ b’ c’ d’ e’ f(a,b,c,d,e) Figure 6.1: Single-error detector for 2-out-of-5 code were changed: Exercise 6.2 Let us use the expressions obtained in Exercise 5.12 only output variables' names s0 = x0y0 cin + x0 y0 cin + x0 y0 cin + x0 y0cin s1 = x1x0 y1 cin + x1y1y0cin + x0x1 y1y0 + x1 x0 y1 cin + x1 y1 y0 cin + x1 x0 y1 y0 + x1 x0 y1 cin + x1 y1 y0 cin + x1 x0 y1 y0 + x1 y1 y0 cin + x1 x0 y1 cin + x1 x0 y1 y0 cout = x1y1 + x1 x0y0 + x0 y1 y0 + y1 y0cin + x0 y1cin + x1 x0 cin + x1 y0 cin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The objective of the design is to reduce the number of gates sharing subnetworks among the outputs, the manipulation of these expressions follows: Solutions Manual - Introduction to Digital Design - February 2, 1999 87 s0 = x0 y0 + x0 y0 cin + x0 y0 + x0 y0 cin = x0  y0  cin + x0  y0 cin = x0  y0   cin s1 = x1 x0 y1cin + y1 y0cin + x0y1 y0 + x0 y1cin + y1 y0 cin + x0 y1y0  +x1 x0 y1 cin + y1 y0 cin + x0 y1 y0 + y1 y0 cin + x0 y1 cin + x0 y1 y0  = x1 y1 A + y1 B  + x1 y1 A + y1 B  = x1 y1 + x1 y1 A + x1 y1 + x1 y1 B = x1  y1  A + x1  y1 B where A = x0 cin + y0 cin + x0 y0 and B = x0 cin + y0 cin + x0 y0 . It can be shown that B = A , and the expressions for s1 becomes: s1 = x1  y1  A For the cout output we obtain: cout = x1 y1 + x1A + y1 A = x1 y1 + A + y1 x1 + A = x1 y1 + y1 A + y1 x1 + x1 A = x1 y1 + x1 y1 A + x1 y1 A = x1 y1 + x1 y1 + x1 y1 A = x1 y1 + x1  y1 A The expression for A can also be transformed to the following more convenient form: A = x0cin + y0 cin + x0y0 = x0 cin + y0  + y0 cin + x0  = x0 cin y0 + y0  + y0 cin x0 + x0  = x0 cin y0 + x0 y0 + y0 cin x0 = x0  y0 cin + x0 y0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The gate network is shown in Figure 6.2 on page 88. Exercise 6.3 A high-level speci cation for this system is: Input: x is a decimal digit represented in BCD. Output: two BCD digits y and z . Function: 10y + z = 3x. From this speci cation we de ne the following switching functions: x3 x2 x1 x0 y3 y2 y1 y0 z3 z2 z1 z0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0000 0000 0000 0001 0001 0001 0010 0010 0010 0000 0011 0110 1001 0010 0101 1000 0001 0100 0111 88 x0 y0 Solutions Manual - Introduction to Digital Design - February 2, 1999 s0 cin A s1 x1 y1 cout Figure 6.2: Network of Exercise 6.2 The simpli ed switching expressions are obtained from K-maps not shown: y3 y1 y0 z3 z2 z1 z0 Exercise 6.4 = = = = = = = y2 = 0 x3 + x2x1 x0 x2 x1 + x2 x0 x2 x1 x0 + x2 x1 x0 x3 + x2x1 x0 + x2 x1 x0 x2 x1 x0 + x2 x1 x0 + x2 x1 x0 x0 0 0 0 0 0 0 0 0 0 0 0 0 0 The NAND; NAND network is shown in Figure 6.3. A high-level speci cation for the system is: Input: A, B , both decimal digits in Excess-3 code. Output: Y 2 fG; E; S g Function: 8 G if A B Y = E if A = B : S otherwise 8 The inputs are represented as A = a3 ; a2 ; a1 ; a0  and B = b3 ; b2 ; b1 ; b0 . The output is encoded as: 0; 0 if A B Y = y1 ; y0 = 0; 1 if A = B : 1; 0 if A B The network could be designed speci cally for the Excess-3 code, in which case it would make use of the corresponding don't cares, or one can use a 4-bit binary comparator. The rst approach might give a simpler network, but it is di cult to design because the simpli cations would require K-maps of eight variables or the use of some tabular minimization technique. Moreover, the Solutions Manual - Introduction to Digital Design - February 2, 1999 89 0 0 x3’ y1 x2 x1 x0 x2 x1’ x2 x0’ x2 x1 x0’ x2’ x1 x0 x2 x1’ x0 x2’ x1 x0’ y3 y2 y0 x2 x1’ x0’ x2’ x1’ x0 x2’ x1 x0’ z1 z3 x3’ x0 z2 z0 Figure 6.3: Network of Exercise 6.3 reduction would be only valid for a two-level network, which is quite complex anyhow because of the eight input variables. Consequently, we design a 4-bit binary comparator. It is an extension to four bits of the 2-bit comparator described in the textbook. Therefore, we can write directly the following switching expressions: Equal = w3 w2w1 w0 Greater = a3 b3 + w3 a2 b2 + w3 w2 a1 b1 + w3 w2 w1 a0b0 where wi = ai bi + ai bi 0 0 0 0 0 0 Due to the code selected, the outputs are y1 = Greater and The network is shown in Figure 6.4. y0 = Equal Exercise 6.5: The modi cation of the network of Example 4.6 is shown in Figure 6.5. Since we are asked to use 4 complex gates 2-AND NOR2, the best solution is to use them on the level that has yi and wi as inputs. The fourth one should not be used to generate z2 since this output is composed of 3 products and the complex gate is able to handle only 2. More logic is required to generate the third product and combine it with the output of the complex gate that would 90 Solutions Manual - Introduction to Digital Design - February 2, 1999 W a3 w3 b3 w3 w2 w1 w0 a3 b3’ w3 a2 b2’ w3 w2 a1 b1’ w3 w2 w1 a0 b0’ y0 a2 b2 a1 b1 a0 b0 W w2 y1 W w1 W w0 Figure 6.4: Network of Exercise 6.4 take care of 2 products. For this reason, it is more interesting to use the fourth complex gate to generate z1 and keep the same structure of gates that was used in Example 4.6 to generate z2 . Although the output of AN3 corresponds to z0 we didn't use its output as the network output to avoid the in uence of the z0 output load on the delay of the other outputs. The network characteristics are: Load factor: 1 Fanout factor: considering F = 12 we have F z2  = F z1  = F z0  = 12 Network size: The NOT gates have size 1 and all others have size 2, thus the network has 23 equivalent gates. The size of the network on Example 4.6 was 38 equivalent gates. Number of levels: 6 Network delays: consider the following table for gate delays: gate Identi er Output Load tpLH ns tpHLns OR3 O1 4 0.27 0.43 NOT N1 N4 3 0.13 0.10 2-AND NOR2 AN2 AN3 3 0.40 0.18 2-AND NOR2 AN4 1 0.25 0.13 2-AND NOR2 AN1 2 0.32 0.16 NOT N2 N3 2 0.10 0.08 NOT N5 L1 0:02 + 0:038L1 0:05 + 0:017L1 AND3 A3 1 0.24 0.20 OR3 O2 L2 0:12 + 0:038L2 0:34 + 0:022L2 The rst critical path we may consider is O1 ! N 1 ! AN 1 ! N 2 ! A3 ! O2 that results in the following delays: TpLH x1 ; z2  = tpHLO1 + tpLH N 1 + tpHLAN 1 + tpLH N 2 + tpLH A3 + tpLH O2 Solutions Manual - Introduction to Digital Design - February 2, 1999 91 y2 w2 x0 x1 x2 y1 w1 y0 w0 O1 N1 2-AND/NOR2 AN1 AN2 AN3 N2 N3 N4 ANx A1 A2 A3 AN4 N6 N5 O2 z1 z2 z0 Figure 6.5: Network for Exercise 6.5 = 0:428 + 0:134 + 0:156 + 0:096 + 0:24 + 0:12 + 0:038L2 = 1:17 + 0:038L2 TpHLx1 ; z2  = tpLH O1 + tpHLN 1 + tpLH AN 1 + tpHLN 2 + tpHLA3 + tpHLO2 = 0:272 + 0:101 + 0:32 + 0:084 + 0:2 + 0:34 + 0:022L2 = 1:32 + 0:022L2 Another path that may be considered is O1 ! N 1 ! AN 2 ! N 3 ! AN 4 ! N 5, that results in the following delays: TpLH x1 ; z1  = tpHLO1 + tpLH N 1 + tpHLAN 2 + tpLH N 3 + tpHL A4 + tpLH N 5 = 0:428 + 0:134 + 0:184 + 0:096 + 0:128 + 0:02 + 0:038L1 = 0:99 + 0:038L1 TpHLx1 ; z1  = tpLH O1 + tpHLN 1 + tpLH AN 2 + tpHLN 3 + tpLH A4 + tpHL N 5 = 0:272 + 0:101 + 0:395 + 0:084 + 0:245 + 0:05 + 0:017L1 = 1:15 + 0:017L1 We can see that the path from x1 to z2 is still the critical path in this circuit, however, the delay was reduced when compared to Example 4.6. Exercise 6.6 : A high-level speci cation for the system is: Input: x; y 2 f0; 1; 2; 3g Output: z 2 fG; E; S g. Function: 8 G if x y z = E if x = y : S if x y We encode the output as follows: 92 Solutions Manual - Introduction to Digital Design - February 2, 1999 G1 E0 S0 From this encoding we write: 0 z z2 z1 z0 0 1 0 0 0 1 z2 = G = x1 y1 + SAME x1 ; y1 x0 y0 z1 = E = SAME x1 ; y1 SAME x0 ; y0  z0 = S = x1 y1 + SAME x1 ; y1 x0 y0 0 0 0 where SAME x; y = xy + x y = x  y . Since xy , x y and SAME x; y are mutually exclusive, the OR operation may be written as an Exclusive-OR operation, as follows: 0 0 0 0 0 z2 = G = x1 y1  x1  y1 x0 y0 z1 = E = x1  y1 x0  y0 z0 = S = x1y1  x1  y1x0 y0 0 0 0 0 0 0 0 0 The NOT gate is implemented using a XOR gate as: x = x  1. Thus, we can transform the above expressions as follows: 0 z2 = G = x1 y1  1  x1  y1  1x0 y0  1 z1 = E = x1  y1  1x0  y0  1 z0 = S = x1  1y1  x1  y1  1x0  1y0 The gate network is shown in Figure 6.6 y1 1 y0 1 x1 1 x0 1 y1’ x1 z2=G y0’ x0 x1’ y1 x0’ y0 x1 z1=E z0=S x0 Figure 6.6: Network for Exercise 6.6 Solutions Manual - Introduction to Digital Design - February 2, 1999 93 Exercise 6.7 Using XOR gates it's possible to get the expressions for equality or di erence: SAME = x  y DIFFERENT = x  y 0 Using these expressions, we obtain the expression for each output, z2 GREATER, z1 EQUAL and z0 LESS as: z2 = DIFFERENT:x + SAME:c2 z1 = SAME:c1 z0 = DIFFERENT:y + SAME:c0 The gate network using XOR and NAND gates is shown in Figure 6.7, on page 93. x’ y SAME z1 c1 c2 x z2 x y DIFFERENT y z0 c0 Figure 6.7: Comparator using XOR and NAND gates Exercise 6.8 The complementer is described by the expressions: zi = xi  c The network that implements a 4-bit complementer using only XOR gates is presented in Figure 6.8, on page 94. Exercise 6.9 The MUX function is de ned as: MUXx; y; s = xs + ys 0 and using this function we want to represent the following functions using muxes: ORa; b = a + b = ab + b = MUXa; 1; b  0 0 NORa; b = a + b = a b = 0:b + a b = MUX0; a ; b 0 0 0 0 0 0 94 Solutions Manual - Introduction to Digital Design - February 2, 1999 c xo x1 x2 x3 z0 z1 z2 z3 Figure 6.8: Complementer using XOR gates NANDa; b; c = NANDa; ANDb; c ANDb; c = bc + 0:c = MUXb; 0; c NANDa; z  = az  = a + z = a z + 1:z = MUXa ; 1; z  Thus NANDa; b; c = MUXa ; 1; MUXb; 0; c 0 0 0 0 0 0 0 0 XORa; b = a  b = a b + ab = MUXa ; a; b 0 0 0 XNORa; b = a  b = ab + a b = MUXa; a ; b 0 0 0 0 From the network in Figure 6.13 we can obtain the following expressions for the selection signal s which controls the rightmost multiplexers, and the output signals z1 and z2 : Exercise 6.10 s = ab + a b = a  b z1 = cs + c s = cs = abc z2 = bs + cs = bab + a b  + cab + a b = ab + ab c + a bc = ab + b c + ba + a c = ab + c + ba + c = ab + ac + bc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 From the boolean expressions we can see that z1 = a  b  c corresponds to the high-level description: z1 = a + b + c mod 2 and z2 = 1 when 2 or more inputs have the value 1. These equations correspond to sum and carry-out outputs of a one-bit adder, with inputs a; b, and c. Solutions Manual - Introduction to Digital Design - February 2, 1999 95 Tree of multiplexers: Part a E a; b; c; d = a b + a b c + bc d + abd + b cd We use Shannon's decomposition to obtain the following four expressions: Exercise 6.11 0 0 0 0 0 0 0 E a; b; 0; 0 E a; b; 0; 1 E a; b; 1; 0 E a; b; 1; 1 = = = = a b + a b + ab = a b + b = a + b ab+ab +b =a +b a b + ab = b a b + b = a + b = ab 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 From these expressions we obtain the tree of multiplexers as shown in Figure 6.9. a’ 1 MUX 1 0 E(a,b,1,1) E(a,b,0,1) 0 1 MUX E(a,b,c,0) 0 b a’ 1 MUX 1 0 E(a,b,0,0) 0 b 1 MUX c d E(a,b,c,1) 1 MUX E(a,b,c,d) b’ c Figure 6.9: Multiplexer tree for E a; b; c; d = a b + a b c + bc d + abd + b cd 0 0 0 0 0 0 0 Part b E a; b; c; d; e; f  = a  b  c  d  e  f Using the same type of decomposition we get the functions shown in the next table: c; d; e; f  E a; b; c; d; e; f  0000 ab 0001 a  b 0010 a  b 0011 ab 0100 a  b ab 0101 ab 0110 0111 a  b 1000 a  b 1001 ab 1010 ab a  b 1011 1100 ab 1101 a  b 1110 a  b 1111 ab 0 0 0 0 0 0 0 0 96 Solutions Manual - Introduction to Digital Design - February 2, 1999 The straight implementation of the tree of multiplexers will look like the network shown in Figure 6.10a. Simplifying the network by removing the repeated terms we obtain the network shown in Figure 6.10b, that looks more like a linear array than a tree, but has the same number of levels and less muxes. s s’ 1 MUX 0 a’ a 1 MUX 0 s=a’b+ab’ c s’ s 1 MUX 0 b a a’ 1 MUX 0 s’ c 1 b MUX s’ s 1 MUX 0 0 c s s’ 1 MUX 0 0 1 d 1 MUX 0 1 MUX E(a,b,c,d,e,f) MUX c s’ s 1 MUX 0 0 1 d 1 MUX 0 e MUX 0 f c s s’ 1 MUX 0 0 1 d e a’ 1 MUX 0 s=a’b+ab’ 1 MUX 0 0 1 MUX 0 1 1 MUX MUX a d E(a,b,c,d,e,f) MUX c s s’ 1 MUX 0 b a a’ 1 MUX 0 0 c s’ 1 MUX 0 1 d 1 MUX 0 e MUX 0 f c s’ s 1 MUX 0 b (a) full multiplexer tree network c d (b) simplified network e c Figure 6.10: Multiplexer network for Exercise 6.11 - part b - E a; b; c; d; e; f  = a  b  c  d  e  f A better multiplexer tree network is realized considering the implementation of the XOR and XNOR functions by multiplexers Exercise 6.9 and the associativity of the XOR function as follows: a  b  c  d  e  f = a  b  c  d  e  f  The network for this case is presented in Figure 6.11. Observe that it has only 3 levels of multiplexers in the critical path and 7 multiplexers. The previous implementation had 5 levels and used 9 multiplexers. Exercise 6.12 From Exercise 6.6, and considering that the input numbers are represented as x = x1 ; x0  and y = y1 ; y0 , we have the following expressions for the outputs x = y E, x y G or x y S: Gx1 ; x0 ; y1 ; y0 = x1 y1 + x0 y1 y0 + x1 x0 y0 0 0 0 0 Solutions Manual - Introduction to Digital Design - February 2, 1999 97 1 a’ a 1 MUX 0 a xor b 0 MUX 1 MUX 0 E(a,b,c,d,e,f) b a a’ 1 MUX 0 1 (a xor b)’ 0 MUX e’ b c’ c e 1 MUX 0 1 MUX 0 e xor f c xor d f d Figure 6.11: Implementation using XOR property to solve Exercise 6.11b - E a; b; c; d; e; f  = abcdef E x1 ; x0 ; y1 ; y0 = x1 y1 + x1 y1 x0 y0 + x0 y0  S x1 ; x0 ; y1 ; y0 = x1 y1 + x0 y1 y0 + x1 x0 y0 0 0 0 0 0 0 0 0 By decomposition we obtain: Gx1 ; x0 ; 0; 0 Gx1 ; x0 ; 0; 1 Gx1 ; x0 ; 1; 0 Gx1 ; x0 ; 1; 1 E x1 ; x0 ; 0; 0 E x1 ; x0 ; 0; 1 E x1 ; x0 ; 1; 0 E x1 ; x0 ; 1; 1 S x1 ; x0 ; 0; 0 S x1 ; x0 ; 0; 1 S x1 ; x0 ; 1; 0 S x1 ; x0 ; 1; 1 = = = = = = = = = = = = x1 + x0 + x1 x0 = x0 + x1 = MUXx0 ; 1; x1  x1 x1x0 = MUXx0 ; 0; x1  0 0 x1 x0 = MUXx0 ; 0; x1  x1 x0 = MUXx0 ; 0; x1  x1 x0 = MUXx0 ; 0; x1  x1 x0 = MUXx0 ; 0; x1  0 0 0 0 0 0 0 0 0 x1 x0 = MUXx0 ; 0; x1  x1 x1 + x0 + x1 x0 = x0 + x1 = MUXx0 ; 1; x1  0 0 0 0 0 0 0 0 0 0 0 0 that corresponds to the network of multiplexers shown in Figure 6.12. 98 Solutions Manual - Introduction to Digital Design - February 2, 1999 x0 0 1 MUX 0 0 x1 x1 1 MUX 0 1 G MUX y1 1 0 x0 1 1 MUX 0 MUX 0 y0 x1’ y1 x0 0 1 MUX 0 1 MUX 0 1 E MUX x1’ x0’ 0 1 MUX 0 0 1 y1 0 MUX y0 x1 x0’ 0 y1 1 MUX 0 1 MUX 0 1 S MUX x1’ x0’ 1 1 MUX 0 y1 x1’ 0 1 MUX 0 0 y0 x1 y1 Figure 6.12: Network for Exercise 6.12 ...
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## This note was uploaded on 03/26/2010 for the course CS 187154200 taught by Professor Ercegovac,m.d. during the Winter '09 term at UCLA.

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