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CSM51Asolution_chapter8

# 24 01 s0 s1 10 10 00 11 01 s2 00 11 s3 x0 s1 1 s2

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Unformatted text preview: bruary 22, 1999 P3 group 1 group 2 group 3 group 4 group 5 group 6 group 7 B 5 3 F 7 4 G 1 1 C 7 7 E 3 3 D,H 11 11 P4 = P3 = fA; B ; F ; G; C ; E ; D; H g The reduced state table is PS A S0 B  S1 C  S2 D; H  S3 E  S4 F  S5 G S6 The state diagram is shown in Figure 8.24. 0/1 S0 S1 1/0 1/0 0/0 1/1 0/1 S2 0/0 1/1 S3 x=0 S1; 1 S2; 1 S3; 0 S0; 0 S5; 0 S3; 1 S0; 1 Input NS,z x=1 S4 ; 0 S5 ; 0 S3 ; 1 S0 ; 1 S5 ; 1 S6 ; 0 S0 ; 0 0/1 1/0 0/1 S6 1/0 S5 0/0 1/1 S4 Figure 8.24: State diagram for Exercise 8.21 We now show that the network performs a serial conversion from BCD to Excess-3. Assume that the initial state is S0 and that the BCD digit x3 ; x2 ; x1 ; x0  is applied with the least signi cant bit x0  rst. From the state diagram following the corresponding paths we get the following table since after a sequence of length four the state is again S0 , we only consider sequences of that length: Solutions Manual - Introduction to Digital Design - February 22, 1999 145 x3 x2 x1 x0 z3 z2 z0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 This corresponds to the desired converter. A timing diagram is x 0000001010011100 State S0 S1 S2 S3 S0 S1 S2 S3 S0 S4 S5 S3 S0 S4 S5 S3 z 1100111000110110 Exercise 8.22 Since the excitation function of a D ip- op is Dt = Qt + 1 is, the D input for each ip- op implementation corresponds to its characteristic function. That for a SR ip- op for a T ip- op for a JK ip- op Dt = Qt + 1 = S + R0 Qt Dt = Qt + 1 = T  Qt Dt = Qt + 1 = QtK 0 + Qt0J The corresponding networks are shown in Figures 8.25. To recognize a sequence with two consecutive 1's followed by one 0 we need to distinguish between the following cases: Exercise 8.23 S2 : S1 : S0 : The corresponding state table is xt , 2 = xt , 1 = 1 Not S2 and xt , 1 = 1 None of the above 146 Solutions Manual - Introduction to Digital Design - February 22, 1999 S D Q Q R CK Q’ Q’ (a) T D Q Q CK Q’ Q’ (b) J Q D K CK Q’ Q Q’ (c) Figure 8.25: Networks of Exercise 8.22 PS S0 S1 S2 To implement these states we need at assignment: Input x=0 x=1 S0 ; 0 S1; 0 S0 ; 0 S2; 0 S0 ; 1 S2; 0 NS,z least two ip- ops. Let us de ne the following state The resulting state table is S0 S1 S2 PS 00 01 10 Q2 Q1 00 01 10 Q 2 Q1 x = 0 x = 1 00,0 01,0 00,0 10,0 00,1 10,0 NS,z Input Solutions Manual - Introduction to Digital Design - February 22, 1999 147 Since the excitation func...
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