35 this network has fewer gates than that of figure

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Unformatted text preview: D0 D Q Q0 x’ Q0 CK Q0’ Q’ Figure 8.34: Modulo-5 counter implemented using D-type ip- ops x0 0 0 1 1 1 1 Q -0 0 0 x0 0 1 Q0 1 0 Q1 J1 : Q1 K1 : x1 x0 1 1 0 0 0 Q -0 0 x1 x0 1 1 0 0 0 Q -0 1 Q1 J0 : Q1 K0 : x1 J1 = x1 x1 which result in the following expressions: Solutions Manual - Introduction to Digital Design - February 22, 1999 159 k1 = x1x0 Q00 + x00 Q0 J0 = x01 K0 = x01 + x00 Q1 The gate network for this exercise is shown in Figure 8.35. This network has fewer gates than that of Figure 8.29 of the text. x0 x1 x1 x0 Q0’ x0’ Q0 x1’ CK x0’ Q1 x0’ x1’ Q0 x1 J CK 1 K Q x1 x0 Q1 x0’ Q1’ z Q’ Q0’ Q0 J CK 0 K Q Q’ Q0’ Figure 8.35: Network for Exercise 8.31 Modulo-3 binary counter using one ip- op per state" approach. The counter has 3 states S 2 f0; 1; 2g, thus 3 ip- ops are required. The state codes are: Exercise 8.32 y2 y1y0 State 001 010 100 0 1 2 The counter changes state when the input x = 1. The state diagram for the counter is shown in Figure 8.36. The switching expressions for the network can be obtained by inspection of the state diagram: Y2 Y1 Y0 z1 z0 = = = = = S1 x + S2 x0 = y1x + y2 x0 y0x + y1 x0 y2x + y0 x0 y2 y1 The corresponding network is shown in Figure 8.37. 160 Solutions Manual - Introduction to Digital Design - February 22, 1999 0 0 0 S0 1 S1 1 1 S2 Figure 8.36: State Diagram for a Modulo-3 Counter y2 x y0 Y0 y0 DQ FF0 Y1 y1 DQ FF1 y1 z0 Y2 y2 DQ FF2 y2 z1 CK Figure 8.37: Modulo-3 counter - Exercise 8.32 Each state is represented by one ip- op. Consider that the input of these FFs are represented as NA; NB; NC; ND; NE; and NF respectively. The switching expressions for these variables are: NA = Fx0 + Bx NB = Ax0 + Cx NC = Bx0 + Cx ND = Cx0 + Ex NE = Dx0 + Fx NF = Ex0 + Ax Exercise 8.33 For the following output encoding the switching expressions for the output are: z0 = Dx0 + Ax + Cx + E a b c z1 z0 00 01 10 Solutions Manual - Introduction to Digital Design - February 22, 1999 161 z1 = Bx + Dx + F The network that corresponds to these expressions is shown in Figure 8.38. B x F C NB A C NC B E ND C F NE D A NF E CK NA A D x’ A z0 C x E DQ FF0 DQ FF1 B DQ FF2 C B D x F z1 DQ FF2 D DQ FF2 E DQ FF2 F Figure 8.38: Network for Exercise 8.33 Exercise 8.34 The sequential network with a shifting state register is shown in Figure 8.39, using a Mealy model. A Moore model implementation would require an extra ip- op. x DQ FF0 DQ FF0 DQ FF0 DQ FF0 CK z Figure 8.39: Network for Exercise 8.34...
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This note was uploaded on 03/26/2010 for the course CS 187154200 taught by Professor Ercegovac,m.d. during the Winter '09 term at UCLA.

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