CSM51Asolution_chapter8

# A switching expression for ci1 is ci1 ci yi k xi0 ci

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Unformatted text preview: : Binary-to-Gray converter Solutions Manual - Introduction to Digital Design - February 22, 1999 131 providing that an = bn = 0. A switching expression for ci+1 is ci+1 = ci yi + k  xi0 ci + yi  The initial condition c0 = 0 is set with INIT = 1. The sequential network is given in Figure 8.12. c INIT i+1 bi ci CK D Q k ai si Figure 8.12: Adder subtractor, Exercise 8.11 Another implementation of this sequential adder subtractor is possible using complementation and addition. This approach will become clear after the discussion in Chapter 10. The state diagram for this sequential network is presented in Figure 8.13, for the case of receiving least signi cant bit and most signi cant bit rst. In each transition we use a pair of bits representing bits from input A at and B bt, respectively. The system output is the same as the state coding used. For both implementation we need three states, coded as: State  y1 ; y 0  EQUAL A = B  00 GREATER A B  01 SMALLER A B  10 a Least-signi cant bit rst: In this case the transition table is: PS Inputs at,bt 00 01 10 11 00 00 10 01 00 01 01 10 01 01 10 10 10 01 10 NS Y1 ; Y0  Exercise 8.12 132 Solutions Manual - Introduction to Digital Design - February 22, 1999 00,11,10 10 EQUAL GREATER 00,11 01 01 LEAST SIGNIFICANT BIT FIRST 10 SMALLER 00,11,01 10 EQUAL GREATER 00,11 01 MOST SIGNIFICANT BIT FIRST SMALLER Figure 8.13: Serial Binary Magnitude Comparator, Exercise 8.12 We can see from the table that: Y1 = y1at0  bt + at0 bt Y0 = y0at0  bt + atbt0 The network is presented in Figure 8.14. b Most-signi cant bit rst: In this case the transition table is: PS Inputs at,bt 00 01 10 11 00 00 10 01 00 01 01 01 01 01 10 10 10 10 10 NS Y1 ; Y0  The new expressions are: 0 Y1 = y1 + y0at0 bt 0 Y0 = y0 + y1atbt0 Solutions Manual - Introduction to Digital Design - February 22, 1999 133 Mem. Cell Y1 y1 a(t) b(t) y0 Y0 y1 y0 CK Figure 8.14: Serial Binary Magnitude Comparator, Exercise 8.12 a These expressions are easily implemented using gates. I...
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