CSM51Asolution_chapter8

CSM51Asolution_chapt - 119 Chapter 8 problem a The minimum delay of the combinational network tp  considered in this problem is obtained by the

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Unformatted text preview: 119 Chapter 8 problem. a The minimum delay of the combinational network tp  considered in this problem is obtained by the following equation tp + 2ns  5ns ! tp  3ns b If the delay of the combinational network can decrease by 30 and the latch delay can decrease by 10, the maximum clock pulse width Tmax  is calculated by the following equation: 0:7tp + 0:9  2ns = 0:7  3 + 1:8 = Tmax ! Tmax = 3:9ns Exercise 8.1 : A minimum clock width of 5 ns and a latch delay of 2 ns are considered in this Using the notation given on Figure 8.15 of the textbook we obtain the following network parameters: Combinational Networks' delays: Exercise 8.2: d1x = d1y = 4  tpgate = 2ns d2 = 1  tp gate = 0:5ns Network set-up time: tx net = ty net = tsucell + d1x = 1 + 2 = 3ns su su Network hold time: Network propagation delay: th net = thcell = 0:5ns tpnet = tpcell + d2 = 3 + 0:5 = 3:5ns Minimal period: Tmin = max tin + tx net; ty net+ tpcell; tp net+ tout  = max 2+3; 3+3; 3:5+2:5 = 6:0ns su su Maximal frequency: fmax = T 1 = 6:0 110,9  167MHz min a There are no races because of the nonoverlapping nature of the two clocks. This assures that in each clock cycle only one state change occurs. b The number of states depends on the mode of operation of the network. We consider two modes. Exercise 8.3 120 Solutions Manual - Introduction to Digital Design - February 22, 1999 i The clock period of the system corresponds to one of the phases say phase 1. In this case, the gated latch loaded during the phase two clock acts just as a temporary bu er to prevent races. The state register corresponds to the register loaded during phase 1. Consequently, the number of states is 2n . The division of the combinational network into two can, in some cases, make sense because of implementation restrictions. For example, if the combinational network is implemented using pass transistors, there is a limitation on the number of them that can be connected in series; in such a case the division in two networks might help. ii The clock period is the time between both clocks phase 1 and phase 2. This results in a system that has a smaller period than that in i and, therefore, in a faster system. In this case each register stores part of the state and the number of potential states is 22n , but these states cannot be utilized in general. The state can be described by two components s1 stored in register 1 and s2 stored in register 2. Each component changes in alternate clock cycles. The output is a combination of two components z1 and z2 expressed as: z1 t = G1s1t; x1 t z2 t = G2s2t; x2 t c Using the rst model, the implementation of the system of Exercise 8.4 Figure 8.40 of the textbook is straightforward if we only replace the D-type cells for two gated latches in a master slave con guration, as shown on page 203 of the textbook. Doing this modi cation, the new design will behave the same way as the one shown in Exercise 8.4, with a slower clock. One way to improve this design would be to split the combinational network, reducing the propagation delay between latches, as shown in Figure 8.1. Observe that one more latch is used in this case. x1 x0’ x0 Y0 x0’ phase 1 phase 2 z y0 Y1 y1 Figure 8.1: Redesign of system in Exercise 8.4 using latches - Exercise 8.3 Solutions Manual - Introduction to Digital Design - February 22, 1999 121 Exercise 8.4 The transition and output functions are described by the following expressions: Y1 = x00 x1 + x0 y1 Y0 = y0x00 + x0 y1 z = y0 y1 y0 00 01 10 11 PS Input x1 x0  00 01 10 11 00 00 10 00 0 01 00 11 00 1 00 11 10 11 0 01 11 11 11 1 NSY1 Y0  Output z  The corresponding state table is for state assignments A = 00; B = 01; C = 10; D = 11 and input coding a = 00; b = 01; c = 10; d = 11 PS A B C D x=a x=b x=c x=d A B A B A A D D C D C D A A D D Inputs NS 0 1 0 1 Output z  The diagram in Figure 8.2 shows the state transitions of this system. The following patterns are recognized by the system assuming that A is the initial state: cb; cbb; cbc; cd; cdc. a,b,d c A/0 a C/0 c b,d b,d a B/1 a c D/1 b,c,d Figure 8.2: State digram for network on Exercise 8.4 122 Exercise 8.5 Solutions Manual - Introduction to Digital Design - February 22, 1999 The state diagram of the pattern recognizer for the sequence 0101011 is shown in Figure 8.3 and has seven states. Each state was labeled with the sequence that it recognizes". We encode these states using three state variables y2 ; y1 ; y0  so that the state assignment of state Si is the radix-2 representation of i. The correspondence between the state assignment and sequence that it detects is shown in the next table. 1/0 0/0 0/0 1/0 0/0 0/0 01 010 1/0 1/0 1/1 0/0 1/0 010101 1/0 0/0 0101 0/0 start 0 01010 Figure 8.3: State diagram for system in Exercise 8.5 State Sequence S0 start S1 0 S2 01 S3 010 S4 0101 S5 01010 S6 010101 The state and transition table is: PS Input x=0 x=1 001,0 000,0 001,0 010,0 011,0 000,0 001,0 100,0 101,0 000,0 001,0 110,0 101,0 000,1 S0 S1 S2 S3 S4 S5 S6 y2 y1y0 000 001 010 011 100 101 110 Y2 Y1Y0 ; z Solutions Manual - Introduction to Digital Design - February 22, 1999 123 The switching expressions for the next state and output are: 0 Y2 = y2y0x0 + y2y0 x + y1 y0 x 0 00 Y1 = y1y0 x + y2y1 y0x0 Y0 = x0 z = y2y1 x These expressions are implemented by AND-OR networks and the state is stored in a 3-bit register. The corresponding sequential network is shown in Figure 8.4. x’ y0’ y2 x y2 y0 x y1 y0 x’ x y1’ y0 x’ y2’ y1 y0’ Y2 Y1 x y2 y1 y0 z Y0 CK Figure 8.4: Network for Exercise 8.5 : The pattern generator for the sequence abcaba is described by the following transition table: PS NS z A Ba B Cb C Dc D Ea E Fb F Aa Let us de ne the following encoding: y2y1 y0 State 000 A z1 z0 001 B 00 a 010 C 01 b 011 D 10 c E 100 101 F Exercise 8.6 124 Solutions Manual - Introduction to Digital Design - February 22, 1999 From the state table and the previous encoding we get the following table and K-maps: PS NS z1 z0 000 001 00 001 010 01 010 011 10 011 100 00 100 101 01 101 000 00 101 - - - - 101 - - - - - y0 y2 Y2: y2 z1 : 0010 0 1 - -  y0 y2 y0 y1 0001 0 0 - -  Y1 : y2 z0 : 0 1 1 0 0 0 - -   y0 y0 The expressions we get from the K-maps are: 0 Y2 = y1y0 + y2y0 00 0 Y1 = y2y1 y0 + y1 y0 0 Y 0 = y0 0 z1 = y1y0 00 0 z0 = y2y1 y0 + y2 y0 The network that implements a canonical version of this sequential network is presented in Figure 8.5 on page 125. The state diagram for this system is presented in Figure 8.6. State S1 represents a 1 followed by a EVEN block of zeros, and state S5 indicates that the system received the required sequence. The corresponding state table is: Input PS x = 0 x = 1 S0 S0 S1 0 S1 S2 S3 0 S1 0 S2 S1 S3 S2 S4 0 S4 S5 S4 0 S5 S4 S1 1 NS outputz  Exercise 8.7 y1 0 1 0 0 0- 1  y1 y2 1 0 - y1 Y0 : 1001 y1 Solutions Manual - Introduction to Digital Design - February 22, 1999 125 Combinational Network Y2 Y1 Y0 y2 cells y1 y0 Comb. Network z1 z0 y1 y0 y2 y0’ y2’ y1’ y0 y2’ y2 y1’ y1 y0’ y0 CK y1 y0’ z1 z0 Figure 8.5: Pattern generator of Exercise 8.6 We use the state code i in binary for the state Si . The PS is represented by the 3-bit vector y2 y1 y0  and the NS by the vector Y2 Y1 Y0 . The output switching expression is: z = y2 y0 The K-maps for the next state bits are shown next. 1 0 S0/0 1 S1/0 0,1 S2/0 0 1 S3/0 0 S1 - block of zeros of EVEN length S5 - block of zeros of ODD length (after correct prefix) 1 1 0 S4/0 0 S5/1 Figure 8.6: State diagram for Exercise 8.7 126 y0 0 1 1 0 0 1 0 0 0 1 y1 Solutions Manual - Introduction to Digital Design - February 22, 1999 y0 0 y2 0 0 0 0 0 1 0 0 1 1 0 y1 0 y2 0 0 1 0 1 0 0 1 1 y0 0 0 y1 1 y2 1 x x x Y2: Y1 : Y0: The switching expression for Y2 ,Y1 , and Y0 are: 0 Y2 = y2 y0 + x0 y2 + xy1y0 00 0 Y1 = y2 y1 y0 + x0 y2y0 00 0 0 0 Y0 = xy2y1 + xy1y0 + y1 y0 + x0 y2 y0 The corresponding sequential network is shown in Figure 8.7. y2 y0’ x’ y2 x y1 y0 y2’ y1’ y0 x’ y2’ y0 x y2’ y1’ x y1’ y0 y1 y0’ x’ y2 y0’ y2 Y2 x x’ Y1 y1 y0 z y0’ CK Y0 y2 y1 y2’ y1’ Figure 8.7: Network for Exercise 8.7 Solutions Manual - Introduction to Digital Design - February 22, 1999 127 We need a 3-bit vector to represent the six states and a 2-bit vector to represent the output. Let us de ne the following encoding: y2y1 y0 State 000 A z1 z0 001 B 00 a C 010 01 b 011 D 10 c E 100 101 F From the state table and the encoding we get the following K-maps. Exercise 8.8 y0 y0 y0 x Y2 : 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 y2 0 x Y1 : 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 y2 0 x Y0 : 1 1 1 1 0 0 0 0 0 0 1 y2 1 y0 0 1 1 1 0 1 y1 0 y2 0 y0 0 0 0 0 1 0 y1 0 y2 1 y1 x z1 : x z0 : y1 y1 The corresponding switching expressions are 0 Y0 = y0 00 0 0 Y1 = x0 y2 y1 y0 + x0y1y0 + xy2 y0 + xy1y0 0 000 Y2 = x0 y2 y0 + x0y1 y0 + xy2y0 + xy2 y1y0 z1 = y2y0 + xy0 0 0 z0 = x0y1y0 + y2 y0 + xy0 The sequential network is shown in Figure 8.8 on page 128. : Direct application of K-maps is not possible for this problem. To design this network it is important to decompose it into smaller parts, as shown in Figure 8.9. The NOTBCD module detects when the input code, or the stored minimum value is not a valid BCD code. The input vector is represented by the vector x = x3 ; x2 ; x1 ; x0 , and the state vector is y = y3 ; y2 ; y1 ; y0 . Input x y is not a valid BCD code if x 9 y 9. This condition is represented by the expression x is not BCD = x3 x2 + x3 x1 y is not BCD = y3 y2 + y3 y1 . The NOTBCD module is implemented by an expression that combines both cases: Exercise 8.9 NOTBCD = x is not BCD + y is not BCD = x3 x2 + x3 x1 + y3 y2 + y3 y1 128 x’ y2 y0’ x’ y1 y0 x y2 y0 x y2’ y1’ y0’ x’ y2’ y1’ y0 x’ y1 y0’ x y2 y0’ x y1 y0 Solutions Manual - Introduction to Digital Design - February 22, 1999 Y2 Y1 Y0 y0’ y2 y2’ y1 y1’ y0 y0’ CK y2 y0 x y0 x’ y1 y0 y2 y0’ x y0’ z1 z0 Figure 8.8: Sequential network for Exercise 8.8 The MIN module is speci ed as: Inputs: x; y 2 f0; 1; 2;    ; 15g Output: z 2 f0; 1; 2;    ; 15g Function: z = x if x y y otherwise The MIN module may be implemented as an iterative array, comparing bits from most-signi cant to least-signi cant. Each bit slice has two data" inputs xi and yi and two carry" inputs ei equal and si xj yj for some j i, and the outputs: mi , ei,1 , and si,1 . The folllowing expressions are used for each output: ei,1 = eixi  yi0 si,1 = si + x0iyiei mi = si,1 xi + s0i,1yi  Solutions Manual - Introduction to Digital Design - February 22, 1999 129 NOTBCD x Y OR y MIN Mem. Cells CLK Figure 8.9: Network for Exercise 8.9 e4 = 1 s4 = 0 The nal gate network for the system is shown in Figure 8.10. : To implement a sequential network that performs a Binary-to-Gray code conversion we use the given equation: gi = bi  bi+1, i = 1; ::::; n , 1 gn = bn Thus, the conversion is done from left to right, storing a new binary-code bit in each clock cycle. Initially the internal variable is 0 bi+1 = 0. The sequential network is shown in Figure 8.11. Exercise 8.10 To perform subtraction it is necessary to have a representation of negative integers, since the result can be negative. Several of these representations are given in Chapter 10. Here we simplify the problem by assuming that the result is positive. Given two n-bit integers represented in the binary number system by x = xn,1 ; : : : ; x0  and y = yn,1 ; : : : ; y0 , and the result represented by sn,1 ; : : : ; s0 , the function to be performed serially in each bit position, for addition and subtraction, is described by the following tables: Exercise 8.11 xi yi ci ci+1 si 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 Addition xi yi bi bi+1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 1 Subtraction si 0 1 1 0 1 0 0 1 130 Solutions Manual - Introduction to Digital Design - February 22, 1999 x3 x2 x3 x1 y3 y2 y3 y1 1 x3 y3 x y 0 MIN slice NOTBCD ei si m y3 e i-1 x2 y2 x1 y1 x0 y0 s i-1 MIN slice MIN slice MIN slice CLK y2 y1 y0 Figure 8.10: Minimum detector for Exercise 8.9 where ci is the carry-in bit at position i, and bi is the borrow-in bit. Let the variable k indicate the operation to be performed as follows: k=  1 for x + y 0 for x , y Since we want to combine both operations in the same module, let us make c = b. A switching expression for the result si is: si = xi  xi  ci for i = 1; : : : ; n , 1 sn = cn BINARY-to-GRAY b bi CLK D Q i+1 g i Figure 8.11: Binary-to-Gray converter Solutions Manual - Introduction to Digital Design - February 22, 1999 131 providing that an = bn = 0. A switching expression for ci+1 is ci+1 = ci yi + k  xi0 ci + yi  The initial condition c0 = 0 is set with INIT = 1. The sequential network is given in Figure 8.12. c INIT i+1 bi ci CK D Q k ai si Figure 8.12: Adder subtractor, Exercise 8.11 Another implementation of this sequential adder subtractor is possible using complementation and addition. This approach will become clear after the discussion in Chapter 10. The state diagram for this sequential network is presented in Figure 8.13, for the case of receiving least signi cant bit and most signi cant bit rst. In each transition we use a pair of bits representing bits from input A at and B bt, respectively. The system output is the same as the state coding used. For both implementation we need three states, coded as: State  y1 ; y 0  EQUAL A = B  00 GREATER A B  01 SMALLER A B  10 a Least-signi cant bit rst: In this case the transition table is: PS Inputs at,bt 00 01 10 11 00 00 10 01 00 01 01 10 01 01 10 10 10 01 10 NS Y1 ; Y0  Exercise 8.12 132 Solutions Manual - Introduction to Digital Design - February 22, 1999 00,11,10 10 EQUAL GREATER 00,11 01 01 LEAST SIGNIFICANT BIT FIRST 10 SMALLER 00,11,01 10 EQUAL GREATER 00,11 01 MOST SIGNIFICANT BIT FIRST SMALLER Figure 8.13: Serial Binary Magnitude Comparator, Exercise 8.12 We can see from the table that: Y1 = y1at0  bt + at0 bt Y0 = y0at0  bt + atbt0 The network is presented in Figure 8.14. b Most-signi cant bit rst: In this case the transition table is: PS Inputs at,bt 00 01 10 11 00 00 10 01 00 01 01 01 01 01 10 10 10 10 10 NS Y1 ; Y0  The new expressions are: 0 Y1 = y1 + y0at0 bt 0 Y0 = y0 + y1atbt0 Solutions Manual - Introduction to Digital Design - February 22, 1999 133 Mem. Cell Y1 y1 a(t) b(t) y0 Y0 y1 y0 CK Figure 8.14: Serial Binary Magnitude Comparator, Exercise 8.12 a These expressions are easily implemented using gates. In order to simplify the design of this system, we decompose the state S t into two components: the number of digits being inserted S1 t, and the correctness of the input S2 t. The rst component is implemented by a modulo-4 counter with states S1 t 2 f0; 1; 2; 3g, and the second component by a two-state machine with states S2 t 2 fY; N g. The output is generated as a function os these states. The initial state is S t = 0; Y , and the combination 0; N  never happens. The state transition table for the two-component system is: Inputs S1 tS2 t x = 0 x = 5 x = 6 others 0Y 1Y 1N 1N 1N 1Y 2N 2Y 2N 2N 1N 2N 2N 2N 2N 3N 3N 3Y 3N 2Y 2N 3N 3N 3N 3N 30Y 0Y 0Y 0Y S1t + 1S2 t + 1 The state diagram for the lock is shown in Figure 8.15. We consider that the counter state S1 t is represented by the vector c1 ; c0 , and S2 t assumes the values 1 for Y and 0 for N . The expression for the next state of the two-state component and the outputs are: Exercise 8.13 S2t + 1 = d0 c01 c00 S2 t + d5 c01 c0 S2 t + d6 c1 c00 S2 t + c1 c0 where di = 1 when x = i. Thus, S2 t + 1 = S2tx03 x02x01x00 c01 c00 + x03 x2x01 x0 c01 c0 + x03x2 x1 x00 c1 c00  + c1 c0 z2 t = c1 c0 S2tx3 x00 0 + S2 t0  = c1 c0 x03 + x0 + S2t0  z1 t = c1 c0 S2tx3 x00 134 Solutions Manual - Introduction to Digital Design - February 22, 1999 8/01 8’/10 0Y 0/00 0’/00 1Y 5/00 5’/00 -/00 2Y 6/00 6’/00 -/00 3Y 1N -/10 2N 3N Figure 8.15: State diagram for lock Exercise 8.13 d0 c1’ c0’ s2(t) s2(t+1) x3 x2 x1 x0 d5 c1’ c0 c1 c0’ D Q d6 CLK Q’ s2(t)’ CLK CNT 1 Modulo-4 Counter 0 c1 c0 c1’ c0’ x3 x0 c1 c0 z2 1 d8 z1 Figure 8.16: Network for lock in Exercise 8.13 The gate network that implements the locker is shown in Figure 8.16. We apply the same concepts presented for the D-latch network on page 200 of the textbook and the master slave con guration shown in Figure 8.11 of the textbook. The general network con guration is shown in Figure 8.17. The slave cell is a D-type latch, as discussed in the book. A combinational network must be designed to activate the set reset inputs of an SR latch. C represents the clock input. Exercise 8.14 The table for the combinational network is shown next: Solutions Manual - Introduction to Digital Design - February 22, 1999 135 SR cell J Comb. Circ. K C R S SR Cell A Q’ Q Figure 8.17: Gate implementation of an edge-triggered JK ip- op C 0 1 1 1 1 1 1 1 1 It is easy to see that J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 S 0 0 0 0 1 1 0 R 0 0 1 0 0 0 1 S = Q0 CJ R = QCK The combinational network is composed of two AND gates only. The timing diagram for the network is shown in Figure 8.18. The timing diagram of the internal signal A, the output of the master module, is also shown. J K C Q A Figure 8.18: Timing diagram for Exercise 8.14 Exercise 8.15 The solution of this exercise is similar to Exercise 8.14, making J = K = T . 136 Exercise 8.16 Solutions Manual - Introduction to Digital Design - February 22, 1999 From the network we obtain the following table, based on the expressions below: JA = KA = xQB JB = KB = x QAQB x = 0 x = 1 x = 0 x = 1 00 01 10 11 0000 0000 0000 0000 0011 1111 0011 1111 00 01 10 11 01 10 11 00 PS Input Input JAKA JB KB NS The outputs are expressed as: z3 = QAQB z2 = QAQ0B z1 = Q0AQB z0 = Q0AQ0B State Name Code S0 00 S1 01 S2 10 11 S3 Giving the following names to the states: we get the transition table: Input Output QA QB x = 0 x = 1 S0 S0 S1 0 S1 S1 S2 1 S2 S2 S3 2 S3 S3 S0 3 NS The state diagram for the given network is presented in Figure 8.19, and corresponds to a modulo-4 counter with decoded output. Exercise 8.17 PS The expression for the ip- op inputs are JA = xQC KA = xQ0B JB = Q0A KB = QA JC = xQB KC = x0 Q0B Solutions Manual - Introduction to Digital Design - February 22, 1999 137 0 1 0 S0/0 S1/1 1 1 S3/3 1 S2/2 0 0 Figure 8.19: State diagram for Exercise 8.16 From the characteristic expressions of the JK ip- op we get the following expressions for the transition functions: QAt + 1 QB t + 1 QC t + 1 z = = = = QAtx0 + QB t + xQ0AtQC t QB tQ0A t + Q0B tQ0At QC tQB t + x + Q0C txQB t Q0C t The corresponding transition table is PS Input Input Output QAQB QC 000 001 010 011 100 101 110 111 00,10,01 00,10,01 00,10,00 00,10,00 00,01,01 00,01,01 00,01,00 00,01,00 x=0 JA KA; JB KB ; JC KC 01,10,00 11,10,00 00,10,10 10,10,10 01,01,00 11,01,00 00,01,10 10,01,10 x=1 x=0 x=1 010 010 010 011 100 100 100 101 010 111 011 111 000 001 101 101 z NS 1 0 1 0 1 0 1 0 To get a high-level description we de ne the following code: 138 Solutions Manual - Introduction to Digital Design - February 22, 1999 QAQB QC state 000 S0 001 S1 010 S2 011 S3 100 S4 S5 101 110 S6 111 S7 The resulting state table is PS Input Output S0 S1 S2 S3 S4 S5 S6 S7 x=0 x=1 S2 S2 S2 S7 S2 S3 S3 S7 S4 S0 S4 S1 S4 S5 S5 S5 NS z 1 0 1 0 1 0 1 0 output sequence pairs the input 0011 22237 11101 The state diagram is shown in Figure 8.20. A timing diagram can be obtained from the following input is arbitrary: xt 0 1 0 1 1 0 0 1 0 1 1 1 0 1 0 st 0 2 3 3 7 5 4 4 0 2 3 7 5 4 0 z 110000111100011 Exercise 8.18 The expressions for the ip- op inputs are TA = QA + Q0B TB = QA + QB The ip- ops change state in every clock pulse depending only on the previous state. The transition table is QAtQB t TAt TB t QA t + 1QB t + 1 00 01 10 11 1 0 1 1 0 1 1 1 10 00 01 00 PS FF inputs NS Let us de ne the following encoding: Solutions Manual - Introduction to Digital Design - February 22, 1999 139 S0/1 0,1 S7/0 1 S1/0 0 0 0,1 S6/1 0 1 1 S5/0 0 1 1 S2/1 1 S3/0 0 S0/1 0 Figure 8.20: State diagram for Exercise 8.17 QAQB 00 01 10 11 The resulting state table is S0 S2 S1 S3 S1 S2 S0 S0 PS NS The state diagram is presented in Figure 8.21. It is an autonomous modulo-3 counter. The expressions for the ip- op inputs and for the output are JA = 1 KA = 1 0 JB = QC KB = 1 JC = QB KC = 1 0 Q0 Q0 z = QA B C The sequential network does not have any input; therefore, the state register changes in each clock pulse depending only on the previous state. The transition table is Exercise 8.19 S0 S1 S2 S3 140 Solutions Manual - Introduction to Digital Design - February 22, 1999 S0 S1 S2 S3 Figure 8.21: State diagram for Exercise 8.18 PS QA tQB tQC t 000 11 11 001 11 01 11 11 010 011 11 01 11 11 100 101 11 01 110 11 11 111 11 01 Let us de ne the following encoding: JAtKA t JB tKB t JC tKC t QA t + 1QB t + 1QC t + 1 01 01 11 11 01 01 11 11 110 100 101 100 010 000 001 000 FF inputs NS Output z t 1 0 0 0 0 0 0 0 QAQB QC state 000 001 010 011 100 101 110 111 A B C D E F G H The resulting transition table is PS A B C D E F G H Let us try to reduce the number of states: P=1 1  NS G E F E C A B A z 1 0 0 0 0 0 0 0 2 A 2  B; C; D; E; F; G; H  2 222121 Solutions Manual - Introduction to Digital Design - February 22, 1999 141 3 11 32333 1 2 3 P3 = A F; H  C  B; D;4 E; G 4 11 2 4434 1 34 5 P4 = A F;2H  C  E B; D; G 5 11 2 3 445 1 345 P5 = A F;2H  C  E G B;6D 5 11 2 3 6 44 1 P2 = A  F; H  2  B; C; D; E; G 3 P6 = P5 = fA; E ; C ; F; H ; G; B; Dg The reduced state table is PS A = S0 E  = S1 C  = S2 F; H  = S3 G = S4 B; D = S5 The state diagram is shown in Figure 8.22. S0/1 S1/0 NS z S1 1 S2 0 S3 0 S0 0 S5 0 S1 0 S2/0 S5/0 S4/0 S3/0 Figure 8.22: State diagram for Exercise 8.19 The network in its equilibrium state produces a 1 every six clock pulses, that is, it implements a modulo-6 frequency divider. Exercise 8.20 The expressions for the ip- op inputs are: The transition table is TA = QA + QB TB = Q0A + QB 142 Solutions Manual - Introduction to Digital Design - February 22, 1999 PS FF inputs NS QAtQB t TAtTB t QAt + 1QB t + 1 00 01 01 01 11 10 10 10 00 11 11 00 Let us de ne the following encoding: QAQB 00 01 10 11 S0 S1 S2 S3 S1 S2 S0 S0 The resulting state table is PS NS S0 S1 S2 S3 The state diagram is shown in Figure 8.23. The network implements an autonomous modulo-3 counter. S0 S1 S2 S3 Figure 8.23: State diagram for Exercise 8.20 Exercise 8.21 The expressions for the ip- op inputs and for the output are S2 R2 J1 K1 T0 z = = = = = = xQ01 + xQ02 Q00 Q2 Q 1 Q0 x0 + Q2  Q0 + Q2 x0 + Q2 + Q1 Q02 + Q01 + Q0 x + Q02 + Q1 + Q00  Q02  Q1 x0 Q00  + Q01 x0 Q0  + Q2  Q1 xQ00  + Q1 xQ0  The transition table is Solutions Manual - Introduction to Digital Design - February 22, 1999 143 Q2 Q1 Q0 000 001 010 011 100 101 110 111 PS 00 00 00 00 00 00 01 01 x=0 00 11 00 11 01 11 01 11 Input 1 1 1 1 1 0 0 1 10 10 10 00 10 10 01 01 x=1 00 01 00 01 01 11 01 11 S2R2 J1 K1 T0 Q2 Q1Q0 000 001 010 011 100 101 110 111 0 0 1 1 1 1 0 1 Input x=0 x=1 001,1 100,0 010,1 101,0 011,0 111,1 000,0 000,1 101,0 101,1 111,1 110,0 000,1 000,0 000,0 000,1 NS,z Let us de ne the following encoding: A B C D E F G H The resulting state table is PS A B C D E F G H x=0 x=1 B,1 E,0 C,1 F,0 D,0 H,1 A,0 A,1 F,0 F,1 H,1 G,0 A,1 A,0 A,0 A,1 NS,z Input Let us try to reduce the number of states. P1 group 1 group 2 A,B,F,G C,D,E,H 0 1221 2111 1 2111 2111 B,F 45 23 G 1 1 C 5 5 D,E,H 121 121 P2 group 1 group 2 group 3 group 4 group 5 0 1 A 2 5 144 0 1 A 2 6 Solutions Manual - Introduction to Digital Design - February 22, 1999 P3 group 1 group 2 group 3 group 4 group 5 group 6 group 7 B 5 3 F 7 4 G 1 1 C 7 7 E 3 3 D,H 11 11 P4 = P3 = fA; B ; F ; G; C ; E ; D; H g The reduced state table is PS A S0 B  S1 C  S2 D; H  S3 E  S4 F  S5 G S6 The state diagram is shown in Figure 8.24. 0/1 S0 S1 1/0 1/0 0/0 1/1 0/1 S2 0/0 1/1 S3 x=0 S1; 1 S2; 1 S3; 0 S0; 0 S5; 0 S3; 1 S0; 1 Input NS,z x=1 S4 ; 0 S5 ; 0 S3 ; 1 S0 ; 1 S5 ; 1 S6 ; 0 S0 ; 0 0/1 1/0 0/1 S6 1/0 S5 0/0 1/1 S4 Figure 8.24: State diagram for Exercise 8.21 We now show that the network performs a serial conversion from BCD to Excess-3. Assume that the initial state is S0 and that the BCD digit x3 ; x2 ; x1 ; x0  is applied with the least signi cant bit x0  rst. From the state diagram following the corresponding paths we get the following table since after a sequence of length four the state is again S0 , we only consider sequences of that length: Solutions Manual - Introduction to Digital Design - February 22, 1999 145 x3 x2 x1 x0 z3 z2 z0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 This corresponds to the desired converter. A timing diagram is x 0000001010011100 State S0 S1 S2 S3 S0 S1 S2 S3 S0 S4 S5 S3 S0 S4 S5 S3 z 1100111000110110 Exercise 8.22 Since the excitation function of a D ip- op is Dt = Qt + 1 is, the D input for each ip- op implementation corresponds to its characteristic function. That for a SR ip- op for a T ip- op for a JK ip- op Dt = Qt + 1 = S + R0 Qt Dt = Qt + 1 = T  Qt Dt = Qt + 1 = QtK 0 + Qt0J The corresponding networks are shown in Figures 8.25. To recognize a sequence with two consecutive 1's followed by one 0 we need to distinguish between the following cases: Exercise 8.23 S2 : S1 : S0 : The corresponding state table is xt , 2 = xt , 1 = 1 Not S2 and xt , 1 = 1 None of the above 146 Solutions Manual - Introduction to Digital Design - February 22, 1999 S D Q Q R CK Q’ Q’ (a) T D Q Q CK Q’ Q’ (b) J Q D K CK Q’ Q Q’ (c) Figure 8.25: Networks of Exercise 8.22 PS S0 S1 S2 To implement these states we need at assignment: Input x=0 x=1 S0 ; 0 S1; 0 S0 ; 0 S2; 0 S0 ; 1 S2; 0 NS,z least two ip- ops. Let us de ne the following state The resulting state table is S0 S1 S2 PS 00 01 10 Q2 Q1 00 01 10 Q 2 Q1 x = 0 x = 1 00,0 01,0 00,0 10,0 00,1 10,0 NS,z Input Solutions Manual - Introduction to Digital Design - February 22, 1999 147 Since the excitation function of a JK ip- op is PS 0 1 NS 01 0- 1-1 -0 JK Input the inputs J1 ; K1 ; J2 , and K2 to the JK ip- ops are Q 2 Q1 x = 0 x = 1 00 01 10 0-,00-,-1 -1,0- PS J2 K2 ; J1 K1 0-,11-,-1 -0,0- Switching expressions for these ip- op inputs are J2 = Q1 x K2 = x0 An expression for the output is J1 = Q02 x K1 = 1 z = Q2 x0 The sequential network is shown in Figure 8.26. Q1 J CK 1 1 CK x K Q’ Q J CK 2 K x’ Q’ Q Q2 z Figure 8.26: Network for Exercise 8.23 Since the output at time t depends on the inputs at time t , 3; t , 2; t , 1, it is necessary to store these in the state register. That is, the register consists of three ip- ops such that Exercise 8.24 Q2 t = xt , 3 Q1 t = xt , 2 Q0 t = xt , 1 148 Solutions Manual - Introduction to Digital Design - February 22, 1999 Consequently, the state description is Q2 t + 1 Q1 t + 1 Q0 t z = = = = Q1 t Q0 t xt xt , 3  xt , 2  xt , 1  xt = Q2  Q1  Q0  x D2 = Q1 D1 = Q0 D0 = x If we use D ip- ops, we get The sequential network is shown in Figure 8.27. Z Q0 X D Q D Q Q1 D Q FF0 Q’ FF1 Q’ FF2 Q’ CK Figure 8.27: Network for Exercise 8.24 Exercise 8.25 We have to store the last input to be able to recognize the sequence 11; therefore, we need: S0 : xt , 1 = 0 S1 : xt , 1 = 1 The state table is PS NS,z Coding S0 as 0 and S1 as 1, the resulting state table is Input PS Q x=0 x=1 0 0,0 1,0 1 0,0 1,1 NS,z S0 S1 x=0 x=1 S0 ; 0 S1; 0 S0 ; 0 S1; 1 Input Solutions Manual - Introduction to Digital Design - February 22, 1999 149 We only need one JK ip- op. Since its excitation function is PS NS 01 1 0- 11 -1 -0 JK the inputs are J=x K = x0 The output is described by z = Qx The sequential network is shown in Figure 8.28. Z X CK J CK K Q’ Q Figure 8.28: Network for Exercise 8.25 Exercise 8.26 The state corresponds to the count. That is, st + 1 = st + 1 mod 3 Using a radix-2 representation for the count we get the following state table PS Input Q 2 Q1 x = 0 x = 1 00 00 01 01 01 10 10 10 00 NS Since the excitation function of a SR ip- op is PS NS 01 0 0- 10 1 01 -0 SR 150 Solutions Manual - Introduction to Digital Design - February 22, 1999 we get the following switching expressions S2 = xQ1 R2 = xQ2 S1 = xQ02Q01 R1 = xQ1 The output is obtained directly from the state register. The sequential network is shown in Figure 8.29. Q2 S CK CK R x Q1 S CK CK R Q’ Q1’ Q Q’ Q2’ Q Figure 8.29: Network for Exercise 8.26 a To design a cyclic counter with the output sequence 0; 1; 3; 7; 6; 4; 0; 1; : : : we need six states. In this rst part, we select the coding so that the output corresponds to the state. The state table is Input PS x=0 x=1 000 000 001 001 001 011 011 011 111 100 100 000 110 110 100 111 111 110 NS = z Since the excitation function of a JK ip- op is PS NS 01 0 0- 11 -1 -0 JK Exercise 8.27 Solutions Manual - Introduction to Digital Design - February 22, 1999 151 we get the following ip- op inputs Q2 Q1 Q0 000 001 011 100 110 111 PS 000-0 -0 -0 x=0 00-0 0-0 -0 Input 0-0 -0 00-0 001-1 -0 -0 x=1 01-0 0-1 -0 J2 K2 J1 K1 J0 K0 1-0 -0 00-1 From K-maps we obtain J2 = xQ1 J1 = xQ0 J0 = xQ02 K2 = xQ01 K1 = xQ00 K0 = xQ2 The sequential network is shown in Figure 8.30. Recall that the output z = z2 ; z1 ; z0  corresponds to the state vector Q2 ; Q1 ; Q0 . z2 z1 J CK 0 K CK x Q’ Q J CK 1 K Q’ Q J CK 2 K Q’ Q z0 Figure 8.30: Network for Exercise 8.27 b In this second case, the state table is PS Input x=0 x=1 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 NS S1 S2 S3 S4 S5 S0 0 1 3 7 6 4 Output with the following encoding for the state: 152 Solutions Manual - Introduction to Digital Design - February 22, 1999 000 001 010 011 100 101 Using the previously given excitation function for a JK ip- op, the ip- ops inputs are PS Input Output Q2Q1 Q0 x=0 x=1 zt 000 0- 0- 0- 0- 0- 1- 000 001 0- 0- -0 0- 1- -1 001 0- -0 0- 0- -0 1- 011 010 011 0- -0 -0 1- -1 -1 111 -0 0- 0- -0 0- 1- 110 100 101 -0 0- -0 -1 0- -1 100 From K-maps we obtain S0 S1 S2 S3 S4 S5 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 For the output, J2 = xQ1 Q0 J1 = xQ02 Q0 J0 = x K2 = xQ0 K1 = xQ0 K0 = x z2 = Q2 + Q1Q0 z1 = Q1 + Q2Q00 z0 = Q1 + Q02Q0 The sequential network is shown in Figure 8.31. A comparison of the networks of Figures 8.30 and 8.31 indicates that solution a results in a simpler network. A modulo-7 up down counter requires seven states. Since the counter is binary, the state assignment is speci ed. The system has two inputs: x the variable to be counted, and c, to control up c = 1 or down c = 0 counting. The state table is Input PS x = 0 x = 1down x = 1up 000 000 110 001 001 001 000 010 010 010 001 011 010 100 011 011 100 100 011 101 101 101 100 110 110 110 101 000 NS = z Exercise 8.28 Solutions Manual - Introduction to Digital Design - February 22, 1999 153 J CK 0 K CK x Q1 Q0 Q2 Q J CK 1 Q J CK 2 Q Q’ K Q’ K Q’ z2 Q2 Q0’ Q1 z1 Q2’ Q0 Q1 z0 Figure 8.31: Network for Exercise 8.27 b a Based on the excitation function for a T ip- op we obtain the following table for ip- op inputs: Input PS Q2Q1 Q0 x = 0 x = 1down x = 1up 000 000 110 001 001 000 001 011 010 000 011 001 011 000 001 111 100 000 111 001 101 000 001 011 110 000 011 110 From K-maps we obtain: T2 T1 T0 The network is shown in Figure 8.32. b using D-type ip- ops the next state is given as input, Qt + 1 = Dt, so the rst table shown in this exercise is used. This time, the next state bits for the case x = 0 have values di erent than zero, and for this reason we need to consider the cases x = 0 and x = 1 separately. Let the inputs of the D-type FFs be D2 ; D1 , and D0 . For the case x = 1, using K-maps, we obtain: D2 x = 1 = Q2 Q0 + Q1 Q0c + Q2 Q01c + Q2 Q1 c0 + Q02 Q01 Q00c0 D1 x = 1 = Q01 Q00 c0 + Q01 Q0 c + Q1 Q0c0 + Q02Q1 Q00 c D0 x = 1 = Q2 Q01 Q00 + Q02 Q00 c + Q1Q00 c0 For x = 0 the expressions for Di are: D2 x = 0 = Q2 D1 x = 0 = Q1 D0 x = 0 = Q0 T2 = xcQ1 Q0 + cQ2 Q1 + c0 Q01 Q00 T1 = xcQ0 + Q2 Q1 + c0 Q00 = xc  Q00  + Q2Q1  T0 = xc + Q2 + Q1 + Q0c0 + Q02 + Q01  154 Solutions Manual - Introduction to Digital Design - February 22, 1999 Combining both cases we obtain the expressions: D2 = Q2 Q0 + Q1 Q0c + Q2 Q01c + Q2 Q1 c0 + Q02 Q01Q00 c0 x + Q2 x0 D1 = Q01 Q00 c0 + Q01 Q0 c + Q1Q0 c0 + Q02 Q1 Q00cx + Q1x0 D0 = Q2 Q01 Q00 + Q02Q00 c + Q1Q00 c0 x + Q0 x0 The network is shown in Figure 8.32. c the implementation of this circuit using a combination of T and D-type ip- ops is a combination of the cases presented in the previous two designs. Considering the two least signi cant state bits stored in T-type FFs and the most-signi cant in a D-type FF, the switching expressions are: D2 = Q2 Q0 + Q1 Q0c + Q2 Q01c + Q2 Q1 c0 + Q02 Q01Q00 c0 x + Q2 x0 T1 = xc  Q00  + Q2Q1  T0 = xc + Q2 + Q1 + Q0 c0 + Q02 + Q01 The network for this case is easily obtained from the other networks given for parts a and b. To recognize the sequence xt , 3; t = 0101 or 0110 we need to distinguish among the following cases: Exercise 8.29 S4 : S3 : S2 : S1 : S0 : The corresponding state table is xt , 3; t , 1 = 011 xt , 3; t , 1 = 010 xt , 2; t , 1 = 01 Not S3 and xt , 1 = 0 None of the above PS Input NS,z Assigning to each state the binary value of its subindex the resulting state table is PS Input Q2Q1Q0 x = 0 x = 1 000 001,0 000,0 001,0 010,0 001 010 011,0 100,0 011 001,0 010,0 100 001,1 000,0 NS,z S0 S1 S2 S3 S4 x=0 S1 ; 0 S1 ; 0 S3 ; 0 S1 ; 0 S1 ; 1 x=1 S0; 0 S2; 0 S4; 0 S2; 1 S0; 0 Solutions Manual - Introduction to Digital Design - February 22, 1999 155 c Q1 Q x c Q2 Q x c’ Q1’ Q0’ x T2 T CK Q Q2 c Q0’ x Q1 Q2 x T1 T CK Q Q1 c Q2 Q1 Q0 c Q2 Q1 Q0 x T0 CK Q0 T Q (a) T-type FF implementation Q1’ Q0’ c’ Q1’ Q0 c Q1 Q0 c’ Q2’ Q1 Q0’ c x x’ Q1 D1 D CK Q Q1 Q2 Q0 Q1 Q0 c Q2 Q1’ c Q2 Q1 c’ Q2’ Q1’ Q0’ c’ x x’ Q2 Q2 Q1’ Q0’ Q2’ Q0’ c Q1 Q0’ c’ D2 D CK Q Q2 x x’ Q0 D0 D CK Q Q0 (b) D-type FF implementation Figure 8.32: Networks for Exercise 8.28 Since the excitation function of a JK ip- op is PS 0 1 NS 01 0- 1-1 -0 JK we determine the inputs J2 ; K2 ; J1 ; K1 ; J1 , and K1 to be 156 Solutions Manual - Introduction to Digital Design - February 22, 1999 Q2 Q1Q0 000 001 010 011 100 PS 0000-1 x=0 00-0 -1 0- Input 1-0 1-0 10010-1 x=1 01-1 -0 0- J2 K2 J1 K1 J0 K0 xQ1 Q00 1 0-1 0-1 0- Using K-maps we get the following switching expressions: J2 K2 J1 K1 J0 K0 The output expression is: = = = = = = xQ0 xQ00 + x0Q0 x0 x The sequential network is shown in Figure 8.33 x Q1 Q0’ x x’ "1" z = x0 Q2 + xQ1 Q0 Q2 J CK 2 Q x’ Q2’ z x Q0 K Q’ x Q1 J Q0 x Q0’ x’ Q0 x’ CK x Q CK 1 K Q’ Q1’ Q0 J CK 0 K Q Q’ Q0’ Figure 8.33: Network for Exercise 8.29 The modulo-5 counter presented in Example 8.8 was implemented using T-type ip- op. For this problem we need to synthesize di erent functions for D-type ip- ops. The transition table, though, is exactly the same. Exercise 8.30 Solutions Manual - Introduction to Digital Design - February 22, 1999 157 Q2Q1 Q0 000 001 010 011 100 PS Input x=0 x=1 000 001 001 010 010 011 011 100 100 000 NS Since the D-type ip- ops has as inputs the bits of the next state shown in the transition table, the K-maps are: Q0 0 1 0 0 0 0 0 1 0 Q -2 0 0 0 0 0 Q0 0 1 1 0 1 Q -2 1 0 0 0 1 Q0 1 0 1 0 0 Q -2 1 x D2 : x D1 : x D0 : Q1 Q1 Q1 The inputs of the D-type ip- ops are: D2 = xQ1Q0 + x0 Q2 D1 = xQ01Q0 + Q1 Q00 + x0 Q1 D0 = xQ02Q00 + x0 Q0 The gate network for the sequential system is presented in Figure 8.34. Comparing Figure 8.34 with Figure 8.28 of the text we can easily see that this implementation uses more gates than the one done with T-type ip- ops. To implement Example 8.9 using JK ip- ops we use the following state transition table and output, that already includes the appropriate input functions for the ip- ops: Exercise 8.31 Q1 Q0 00 01 10 11 PS 01 01,0 00,0 11,0 10,0 Input 10 10,1 11,1 10,0 00,0 NS, z 11 10,0 11,0 00,1 11,1 01 0-101 -01-0-1 J1 K1 J0 K0 Input 10 1-010 -00-1-1 11 1-010 -10-0-0 The Kmaps for the combinational circuit that activates the JK inputs of the ip- ops are: 158 Solutions Manual - Introduction to Digital Design - February 22, 1999 x Q1 Q0 x’ Q2 D2 D Q Q2 CK Q2’ Q’ x Q1’ Q0 Q1 Q0’ x’ Q1 D1 D Q Q1 CK Q1’ Q’ x Q2’ Q0’ D0 D Q Q0 x’ Q0 CK Q0’ Q’ Figure 8.34: Modulo-5 counter implemented using D-type ip- ops x0 0 0 1 1 1 1 Q -0 0 0 x0 0 1 Q0 1 0 Q1 J1 : Q1 K1 : x1 x0 1 1 0 0 0 Q -0 0 x1 x0 1 1 0 0 0 Q -0 1 Q1 J0 : Q1 K0 : x1 J1 = x1 x1 which result in the following expressions: Solutions Manual - Introduction to Digital Design - February 22, 1999 159 k1 = x1x0 Q00 + x00 Q0 J0 = x01 K0 = x01 + x00 Q1 The gate network for this exercise is shown in Figure 8.35. This network has fewer gates than that of Figure 8.29 of the text. x0 x1 x1 x0 Q0’ x0’ Q0 x1’ CK x0’ Q1 x0’ x1’ Q0 x1 J CK 1 K Q x1 x0 Q1 x0’ Q1’ z Q’ Q0’ Q0 J CK 0 K Q Q’ Q0’ Figure 8.35: Network for Exercise 8.31 Modulo-3 binary counter using one ip- op per state" approach. The counter has 3 states S 2 f0; 1; 2g, thus 3 ip- ops are required. The state codes are: Exercise 8.32 y2 y1y0 State 001 010 100 0 1 2 The counter changes state when the input x = 1. The state diagram for the counter is shown in Figure 8.36. The switching expressions for the network can be obtained by inspection of the state diagram: Y2 Y1 Y0 z1 z0 = = = = = S1 x + S2 x0 = y1x + y2 x0 y0x + y1 x0 y2x + y0 x0 y2 y1 The corresponding network is shown in Figure 8.37. 160 Solutions Manual - Introduction to Digital Design - February 22, 1999 0 0 0 S0 1 S1 1 1 S2 Figure 8.36: State Diagram for a Modulo-3 Counter y2 x y0 Y0 y0 DQ FF0 Y1 y1 DQ FF1 y1 z0 Y2 y2 DQ FF2 y2 z1 CK Figure 8.37: Modulo-3 counter - Exercise 8.32 Each state is represented by one ip- op. Consider that the input of these FFs are represented as NA; NB; NC; ND; NE; and NF respectively. The switching expressions for these variables are: NA = Fx0 + Bx NB = Ax0 + Cx NC = Bx0 + Cx ND = Cx0 + Ex NE = Dx0 + Fx NF = Ex0 + Ax Exercise 8.33 For the following output encoding the switching expressions for the output are: z0 = Dx0 + Ax + Cx + E a b c z1 z0 00 01 10 Solutions Manual - Introduction to Digital Design - February 22, 1999 161 z1 = Bx + Dx + F The network that corresponds to these expressions is shown in Figure 8.38. B x F C NB A C NC B E ND C F NE D A NF E CK NA A D x’ A z0 C x E DQ FF0 DQ FF1 B DQ FF2 C B D x F z1 DQ FF2 D DQ FF2 E DQ FF2 F Figure 8.38: Network for Exercise 8.33 Exercise 8.34 The sequential network with a shifting state register is shown in Figure 8.39, using a Mealy model. A Moore model implementation would require an extra ip- op. x DQ FF0 DQ FF0 DQ FF0 DQ FF0 CK z Figure 8.39: Network for Exercise 8.34 ...
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This note was uploaded on 03/26/2010 for the course CS 187154200 taught by Professor Ercegovac,m.d. during the Winter '09 term at UCLA.

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