CSM51Asolution_chapter8

Considering the two least signi cant state bits

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Unformatted text preview: expressions: D2 = Q2 Q0 + Q1 Q0c + Q2 Q01c + Q2 Q1 c0 + Q02 Q01Q00 c0 x + Q2 x0 D1 = Q01 Q00 c0 + Q01 Q0 c + Q1Q0 c0 + Q02 Q1 Q00cx + Q1x0 D0 = Q2 Q01 Q00 + Q02Q00 c + Q1Q00 c0 x + Q0 x0 The network is shown in Figure 8.32. c the implementation of this circuit using a combination of T and D-type ip- ops is a combination of the cases presented in the previous two designs. Considering the two least signi cant state bits stored in T-type FFs and the most-signi cant in a D-type FF, the switching expressions are: D2 = Q2 Q0 + Q1 Q0c + Q2 Q01c + Q2 Q1 c0 + Q02 Q01Q00 c0 x + Q2 x0 T1 = xc  Q00  + Q2Q1  T0 = xc + Q2 + Q1 + Q0 c0 + Q02 + Q01 The network for this case is easily obtained from the other networks given for parts a and b. To recognize the sequence xt , 3; t = 0101 or 0110 we need to distinguish among the following cases: Exercise 8.29 S4 : S3 : S2 : S1 : S0 : The corresponding state table is xt , 3; t , 1 = 011 xt , 3; t , 1 = 010 xt , 2; t , 1 = 01 Not S3 and xt , 1 = 0 None of the above PS Input NS,z Assigning to each state the binary value of its subindex the resulting state table is PS Input Q2Q1Q0 x = 0 x = 1 000 001,0 000,0 001,0 010,0 001 010 011,0 100,0 011 001,0 010,0 100 001,1 000,0 NS,z S0 S1 S2 S3 S4 x=0 S1 ; 0 S1 ; 0 S3 ; 0 S1 ; 0 S1 ; 1 x=1 S0; 0 S2; 0 S4; 0 S2; 1 S0; 0 Solutions Manual - Introduction to Digital Design - February 22, 1999 155 c Q1 Q x c Q2 Q x c’ Q1’ Q0’ x T2 T CK Q Q2 c Q0’ x Q1 Q2 x T1 T CK Q Q1 c Q2 Q1 Q0 c Q2 Q1 Q0 x T0 CK Q0 T Q (a) T-type FF implementation Q1’ Q0’ c’ Q1’ Q0 c Q1 Q0 c’ Q2’ Q1 Q0’ c x x’ Q1 D1 D CK Q Q1 Q2 Q0 Q1 Q0 c Q2 Q1’ c Q2 Q1 c’ Q2’ Q1’ Q0’ c’ x x’ Q2 Q2 Q1’ Q0’ Q2’ Q0’ c Q1 Q0’ c’ D2 D CK Q Q2 x x’ Q0 D0 D CK Q Q0 (b) D-type FF implementation Figure 8.32: Networks for Exercise 8.28 Since the excitation function of a JK ip- op is PS 0 1 NS 01 0- 1-1 -0 JK we determine the inputs J2 ; K2 ; J1 ; K1 ; J1 , and K1 to be 156 Solutions Manual - Introduction to Digital Design - February 22, 1999 Q2 Q1Q0 000 001 010...
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