Unformatted text preview: n order to simplify the design of this system, we decompose the state S t into two components: the number of digits being inserted S1 t, and the correctness of the input S2 t. The rst component is implemented by a modulo-4 counter with states S1 t 2 f0; 1; 2; 3g, and the second component by a two-state machine with states S2 t 2 fY; N g. The output is generated as a function os these states. The initial state is S t = 0; Y , and the combination 0; N never happens. The state transition table for the two-component system is: Inputs S1 tS2 t x = 0 x = 5 x = 6 others 0Y 1Y 1N 1N 1N 1Y 2N 2Y 2N 2N 1N 2N 2N 2N 2N 3N 3N 3Y 3N 2Y 2N 3N 3N 3N 3N 30Y 0Y 0Y 0Y S1t + 1S2 t + 1 The state diagram for the lock is shown in Figure 8.15. We consider that the counter state S1 t is represented by the vector c1 ; c0 , and S2 t assumes the values 1 for Y and 0 for N . The expression for the next state of the two-state component and the outputs are:
Exercise 8.13 S2t + 1 = d0 c01 c00 S2 t + d5 c01 c0 S2 t + d6 c1 c00 S2 t + c1 c0
where di = 1 when x = i. Thus, S2 t + 1 = S2tx03 x02x01x00 c01 c00 + x03 x2x01 x0 c01 c0 + x03x2 x1 x00 c1 c00 + c1 c0 z2 t = c1 c0 S2tx3 x00 0 + S2 t0 = c1 c0 x03 + x0 + S2t0 z1 t = c1 c0 S2tx3 x00 134 Solutions Manual - Introduction to Digital Design - February 22, 1999 8/01 8’/10 0Y 0/00 0’/00 1Y 5/00 5’/00 -/00 2Y 6/00 6’/00 -/00 3Y 1N -/10 2N 3N Figure 8.15: State diagram for lock Exercise 8.13 d0 c1’ c0’ s2(t) s2(t+1) x3 x2 x1 x0 d5 c1’ c0 c1 c0’ D Q d6 CLK Q’ s2(t)’ CLK
CNT 1 Modulo-4 Counter 0 c1 c0 c1’ c0’ x3 x0 c1 c0 z2 1 d8 z1 Figure 8.16: Network for lock in Exercise 8.13 The gate network that implements the locker is shown in Figure 8.16. We apply the same concepts presented for the D-latch network on page 200 of the textbook and the master slave con guration shown in Figure 8.11 of the textbook. The general network con guration is shown in Figure 8.17. The slave cell is a D-type latch, as discussed in the book. A combinational network must be designe...
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- Winter '09
- Nondeterministic finite state machine, State transition table