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Ii the clock period is the time between both clocks

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Unformatted text preview: the division in two networks might help. ii The clock period is the time between both clocks phase 1 and phase 2. This results in a system that has a smaller period than that in i and, therefore, in a faster system. In this case each register stores part of the state and the number of potential states is 22n , but these states cannot be utilized in general. The state can be described by two components s1 stored in register 1 and s2 stored in register 2. Each component changes in alternate clock cycles. The output is a combination of two components z1 and z2 expressed as: z1 t = G1s1t; x1 t z2 t = G2s2t; x2 t c Using the rst model, the implementation of the system of Exercise 8.4 Figure 8.40 of the textbook is straightforward if we only replace the D-type cells for two gated latches in a master slave con guration, as shown on page 203 of the textbook. Doing this modi cation, the new design will behave the same way as the one shown in Exercise 8.4, with a slower clock. One way to improve this design would be to split the combinational network, reducing the propagation delay between latches, as shown in Figure 8.1. Observe that one more latch is used in this case. x1 x0’ x0 Y0 x0’ phase 1 phase 2 z y0 Y1 y1 Figure 8.1: Redesign of system in Exercise 8.4 using latches - Exercise 8.3 Solutions Manual - Introduction to Digital Design - February 22, 1999 121 Exercise 8.4 The transition and output functions are described by the following expressions: Y1 = x00 x1 + x0 y1 Y0 = y0x00 + x0 y1 z = y0 y1 y0 00 01 10 11 PS Input x1 x0  00 01 10 11 00 00 10 00 0 01 00 11 00 1 00 11 10 11 0 01 11 11 11 1 NSY1 Y0  Output z  The corresponding state table is for state assignments A = 00; B = 01; C = 10; D = 11 and input coding a = 00; b = 01; c = 10; d = 11 PS A B C D x=a x=b x=c x=d A B A B A A D D C D C D A A D D Inputs NS 0 1 0 1 Output z  The diagram in Figure 8.2 shows the state transitions of this system. The following patterns are recognized...
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