# lab4 - ECE 3150 Lab 4 THE MOS DIFFERENTIAL PAIR 1...

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ECE 3150 Lab 4 3/26/2010 T HE MOS D IFFERENTIAL P AIR 1 Objectives In this lab, you will examine the current–voltage characteristics of a MOS differential pair , which is widely used as an input stage in operational amplifiers and in many other types of circuits as well. This venerable circuit has a relatively large response to a change in the difference between its two input voltages, but a relatively small response to a change in the average value of its two input voltages. Like the cascode amplifier, it has its origin in the days of the vacuum tube. It can be traced back to Fig. 3 of British Patent Specification 482,740 filed by A. D. Blumlein on July 4, 1936. In 2001, the differential pair was informally voted as the top analog circuit of all time in a top-ten list of analog circuits at the International Solid-State Circuits Conference during an evening panel discussion. 2 Prelab The following prelab questions have been constructed to help you prepare to do the lab efficiently. Unless otherwise stated, you should assume that like transistors are matched. Consider the circuit shown in Fig. 1a, comprising three n MOS transistors. The sources of M 1 and M 2 , which are called the differential- pair transistors , are connected together at node V . The third transistor, M b , which is called the bias transistor , is supposed to sink a constant bias current, I b , from node V . The gate voltages of M 1 and M 2 are the inputs to this circuit and the currents I 1 and I 2 are its outputs. For a circuit like the differential pair, we often express each of the two input voltages, V 1 and V 2 , in terms of a common-mode input voltage, V cm =(V 1 +V 2 )/2 , and a differential-mode input voltage, V dm =(V 1 - V 2 )/2 . Analogously, we also often express the two output currents, I 1 and I 2 , in terms of a common-mode output current, I cm =(I 1 +I 2 )/2 , and a differential-mode output current, I dm =(I 1 - I 2 )/2 . 1. Suppose that M, M 2 and M 3 are well matched, that V out1 and V out2 are high enough to keep all transistors in saturation, and that the Early effect is negligible. If V 1 =V 2 =V cm , what is the relationship that holds among I 1 , I 2 and I b ? 2. Use V Dsat = V GS – V th to find an expression for the common-source node voltage, V , in terms of V b and V 1 =V 2 =V cm , that is valid for all transistors above threshold. If we would like M b to operate in saturation, what is the minimum allowable value of V cm ? For the value of V cm above this minimum, what is the minimum allowable value for V out1 and V out2 if M 1 and M 2 are to remain in saturation?

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