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week14

# week14 - ECE 3150 Spring 2009 Week 14 Recitation There is...

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ECE 3150 Spring 2009 Week 14 Recitation There is Homework 10 due on Friday. Additional practice problems: (a) What is the logic function of Out ? (b) Design the full complementary CMOS logic with PUN and PDN that implements the same function. Indicate sizing of each transistor so that the logic network will match the large signal resistance of the inverter of size (1p, 1n) in Prob. 3. A B C D Out Out=AC +BD 1

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(c) Design PTL with inverters for the same function. What are the input logic values that will generate an uncertain (high-impedance) output signal? A weak logic signal? What are the main problems for the circuit you have design? Suggest a way to remove the possible weak “1” at the output. High-impedance values: A = 0 or B = 0 . Weak logic values: ( A = 1 and C = 0 ); ( B = 1 and D = 0 ) We can add a level restorer and a staticizer to remove the possible weak 1’s. (d) Design a DCVSL circuit, assuming all complements of A, B, C , and D are available. Will there be a weak value at the output?
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