HW2 - HOMEWORK #2 ECE 4750/CS 4420 Computer Architecture...

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Unformatted text preview: HOMEWORK #2 ECE 4750/CS 4420 Computer Architecture Due Thursday, November 5th at midnight (11:59pm) Problem 2.1 Advanced Memory Hierarchy [25 points] You are trying to determine what sort of cache structure to use for this 8-bit computer. There are two kinds of cache designs to consider. Cache D is a direct-mapped cache with 4 lines with 16 bytes/line. Cache F is fully associative, using a least recently used replacement policy, with 4 lines with 16 bytes/line. Addresses are 12 bits long and are byte addresses. On a hit, the access takes 1 cycle. On a miss, it takes 30 cycles. (a) In the following chart, mark the part of the address used for the tag, the line index, and the offset within the line. 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 Cache D: Cache F: (b) You are testing the cache by accessing the following sequence of hexadecimal byte addresses, starting with empty caches. Complete the following tables for both Cache D and F showing the progression of cache contents as accesses occur (in the tables, inv = invalid, and the column of a particular cache line contains the {tag,index} contents of that line; e.g. for the address 110, L1 gets the value 11). You only need to fill in elements in the table when a value changes. Part b) Part c) line in cache line Cache D Address L0 L1 L2 L3 hit? VC VC hit? 0x110 inv 11 inv inv no inv no 0x101 10 0x123 12 0x201 20 10 0x15C 0x102 0x136 0x202 0x137 0x124 0x103 0x15D 0x203 Cache D Cache D with Victim Cache Total Misses Total Cycles Part b) Part c) line in cache line Cache F Address L0 L1 L2 L3 hit? VC VC hit? 0x110 11 inv inv inv no inv no 0x101 10 0x123 12 0x201 20 0x15C 0x102 0x136 0x202 0x137 0x124 0x103 0x15D 0x203 Cache F Cache F with Victim Cache Total Misses Total Cycles (c) In order to improve performance, you have decided to add a victim cache. This will be one line of 16 bytes that always holds the most recently evicted line from the main cache. When an item is found in the victim cache, it takes 2 cycles to bring it back into the main cache and return it. Fill out the remaining tables above. (d) What is the difference in hit rate between Cache F with the victim cache and a fully associative cache with 5 lines instead of 4? What is the difference in average access time? Explain your answers. (e) Let us consider adding virtual memory with 32-byte pages to the memory hierarchy. For the direct-mapped cache configuration, which block(s) can virtual (byte) address 0x034 be mapped to? Consider both virtually indexed and physically indexed cases for each configuration, and enumerate all possible blocks.) Virtually indexed Physically indexed Direct-mapped Part b) Part c) line in cache line Cache F Address L0 L1 L2 L3 hit?...
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HW2 - HOMEWORK #2 ECE 4750/CS 4420 Computer Architecture...

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