HW3-sol - HOMEWORK #3 ECE 4750/CS 4420 Computer...

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HOMEWORK #3 ECE 4750/CS 4420 – Computer Architecture Due Thursday, November 30 th at midnight Problem 3.1 Register Lifetime [25 points] (a) Instruction # Src1 RL Bit Src2 RL Bit I 1 X I 2 I 3 X X I 4 X I 5 I 6 I 7 X I 8 (b) We can free a physical register when an instruction that writes to the corresponding architecture register commits. With RL bits, we can now free a physical register when an instruction that has the corresponding architectural register's RL bit set commits. If you assume that there is no instruction following the given sequence, you can also check Src2 for I4 and I7, and Src1 for I8. (c) Sequence A, B and D can potentially make earlier progress with the use of RL bits. In Sequence A, we can now reuse a physical register after I 3 commits instead of some instruction afterwards that writes to r2. For Sequence B, we can now free a physical register after I 1 commits, instead of waiting for I 3 to commit (which would have to wait for a long latency operation to occur. ..this sequence is perhaps the most likely to be helped out). Sequence C is not helped by RL bits, since either way we have to wait until I 2 commits. Finally, for Sequence D, we can free the register after I 2 commits, instead of waiting for I 3 , which could potentially be waiting on a dependency to r5 .
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Problem 3.2 Multiple Issue Processors [25 points]
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This note was uploaded on 03/26/2010 for the course ECE 4750 taught by Professor Suh during the Spring '07 term at Cornell University (Engineering School).

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HW3-sol - HOMEWORK #3 ECE 4750/CS 4420 Computer...

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