prelim09sol - NAME:_ NetID:_ ECE4750 / CS4220 Fall 2009...

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NAME:___________________________________ NetID:_______________________ 1 ECE4750 / CS4220 Fall 2009 Prelim Solution Question 1 [4 pts] NRE cost is increasing for more advanced fabrication technologies. Question 2 [4 pts] Machine A: 600 / 1.5 = 400 million instructions / second Æ 5 seconds Machine B: 1000 / 2 = 500 million instructions / second Æ 4 seconds Question 3 [4 pts] Use geometric means. For normalized execution time, other means change depending on the baseline system. Question 4 [5 pts] 100-cores: 1 / (0.9/100 + 0.1) = 1 / 0.109 50-cores + 1 fast core: 1 / (0.9/60 + 0.1/10) = 1 / 0.025 = 40 Question 5 [4 pts] There is a new structural hazard between a load in the MEM stage and an instruction in the IF stage Example: LD L D L D L D Question 6 [4 pts] The branch delay slot was featured in MIPS architectures because it took 1 cycle to resolve the branch and it was not difficult to find an independent instruction that could be executed in the meantime. Later architectures feature deeper pipelines, which increased the number of cycles before branch resolution, and superscalar processing, which increased the number of scheduling slots each cycle, so given massively increasing amount of pipeline bubbles after a branch, it made less sense to try to schedule independent instructions into these slots. - The number of branch delay slots to hide the pipeline bubbles change with advances in the pipeline Question 7 [6 pts] What are the penalties (the number of pipeline bubbles) for a taken branch? 4 bubbles
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prelim09sol - NAME:_ NetID:_ ECE4750 / CS4220 Fall 2009...

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