Handout_3_-_Resistive_Network

Handout_3_-_Resistive_Network - 1 EE 101A / Winter 10...

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Unformatted text preview: 1 EE 101A / Winter 10 Handout #3 EE 101A Resistive Network Reference – Hambley, Chapter 1.4 - 1.5, 1.7, 2.1 – 2.4 1. Kirchoff’s Law 1.1 Kirchoff’s Current Law (KCL) A node with N branches N I K = 0 K = 1 No charge can accumulate at a node. I 1 I N I 2 I N-1 … I 1 I N I 2 I N-1 … 2 Example 3 Circuits that violate KCL In general, series connection of current sources with different magnitudes is not allowed. 1.2 Kirchoff’s Voltage Law (KVL) A loop with N elements N V K = 0 K = 1 No voltage can develop across a node. Example 1 A 1 A 2 A 2 A 3 A 2 A 1 A 3 A + +--- +- + Node N Node 1 V N V N-1 V 2 V 1 + +--- +- + Node N Node 1 V N V N-1 V 2 V 1 4 5 Circuits that violate KVL In general, parallel connection of voltage sources of different magnitudes is not allowed. 2. Circuit Analysis To systematically analyze a circuit : a. define all voltages and currents across all elements b. write I-V characteristics for all elements c. write KCL for all nodes (except ground) d. write KVL for all (independent) loops...
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This note was uploaded on 03/30/2010 for the course EE 101A taught by Professor Wong during the Winter '08 term at Stanford.

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Handout_3_-_Resistive_Network - 1 EE 101A / Winter 10...

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