chap3 - William Stallings Computer Organization and...

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William Stallings Computer Organization and Architecture Chapter 3 A top-level view of computer function and interconnection
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Computer Components: Top Level View ALU Control unit ……
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& U/ ” = ±± & ♥☛ CPU , CPU IR CPU =, CPU ⑤ ❺ ➘ CPU ⑤ ❺ =,
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Machine language    C=2* π *R Memory   CPU 1000 LDA 2000 1001 MPY 2001 1002 MPY 2002 1003 STA 2003 2000 2 2001 3.14 2002 6.5 2003 1000 LDA 2000 PC IR AC ALU control unit …… I/O module 1 2 π r
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MPY pi Instruction interpreter ALU data data result * general-purpose General purpose hardware IR Control unit AC AC Control signal MBR
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Add e Instruction interpreter ALU data data result + general-purpose General purpose hardware IR Control unit AC AC MBR
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Program Concept General purpose hardware can do different  tasks, given correct  control signals Supply a set of control signals (instructions) Program is a sequence of instructions
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Instruction Cycle (simplify) MPY   pi Two steps: Fetch Execute
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Fetch Cycle Program Counter (PC) holds address of next  instruction to fetch Processor  fetches  instruction from memory  location pointed to by PC Instruction  loaded  into Instruction Register (IR) Increment PC Unless told otherwise Processor  interprets  instruction 3
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Execute cycle (different operations) Performs required actions  (fall into  4 categories )  : Processor-memory LDA 2000” data transfer between CPU and main memory Processor - I/O “load I/O  5” Data transfer between CPU and I/O module Data processing “MPY   2001”   Some arithmetic or logical operation on data Control “jump  1000” Alteration of sequence of operations e.g. jump
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Example of Program Execution 1 – load 2 – store 5 – add FI EI P56
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Memory   CPU 1000 LDA 2000 1001 MPY 2001 1002 MPY 2002 1003 STA 2003 2000 2 2001 3.14 2002 6.5 2003 1001 PC IR AC ALU control unit MAR MBR r c=2 π r data address I/O MPY 2001 3.14 * MPY 2001 (detailed look) 2 ADD AX, A[S i ]
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Instruction Cycle State Diagram (detailed look) 12.4
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W& : CPU ´ ♥☛ ( , ´ „ “ * ),  ´ „ “ ? ´ „ MSN,  ´„ “ * ? MSN ui r + . : * ui r + , CPU ´„“ * uir + .
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Interrupts Interrupt from peripheral:  CPU CPU I/O memory complete or 1 parity error from I/O, . .. * Running a progrsm timer P58 xx W &
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What is interrupt? It is a  mechanism  by which other modules (e.g. I/O) may interrupt normal sequence of processing Why interrupt? -- may handle exception event: incoming data,. . -- improve performance: parallelism -- time-sharing (web server) Review language component
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Multi-programmed I/O devices very slow 20ns 60ns 12ms CPU Cache Memory Disk 3GHz 800MHz 3 times 1,000,000 times Printer 1 1
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Classes of Interrupts Program e.g. overflow, division by zero,  system call I/O from I/O controller Hardware failure e.g. memory parity error Timer Generated by internal processor timer OS uses it  How distinguish them?  Interrupt number
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Program Flow Control wait wait * * P60
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chap3 - William Stallings Computer Organization and...

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