chap5 - William Stallings Computer Organization and...

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William Stallings Computer Organization and Architecture Chapter 5 Internal Memory
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word byte address: capacity Memory (RAM) 0: 2 32 -1: addressable? :2 32 -1
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Characteristics of memory systems Location P97 Capacity Unit of transfer Access method Performance Physical type:  magnetic, optical, semiconductor Physical characteristics: volatile? Organisation
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Location CPU Internal External
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Components   memory CPU I/O System bus I/O ALU Control unit registers program data Disk controller cache cache L1 L2 disk
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Capacity Word size The natural unit of organisation Number of words or Bytes
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Unit of Transfer Internal Usually governed by data bus width External Usually a block which is much larger than a word   ? Addressable unit (of transfer) Smallest location which can be uniquely addressed Word internally Cluster on M$ disks
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Access Methods  
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Access Methods (1) Sequential Start at the beginning and read through in order Access time depends on location of data and  previous location e.g. tape Direct Individual blocks have unique address Access is by jumping to vicinity plus sequential  search Access time depends on location and previous  location e.g. disk
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Access Methods (2) Random Individual addresses identify locations exactly Access time is independent of location or previous  access e.g. RAM (Random Access Memory) Associative Data is located by a comparison with contents of a  portion of the store Access time is independent of location or previous  access e.g. cache
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Unique wired-in addressing mechanism Difference between direct and random access 0 1 2 k -1 Shared R/W mechanism Unique wired-in addressing mechanism
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Memory Hierarchy Registers In CPU Internal or Main memory May include one or more levels of cache “RAM” External memory Backing store
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Memory Hierarchy - Diagram
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Performance Memory cycle  describes the performance of  internal Memory Meaning of  memory cycle time  (for RAM) the time it takes to  perform a read or write  operation  + additional time required before a  second access can commence  Memory cycle time =  access time  + recovery time
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Performance Access time (s/1 ) ~  Memory cycle time (ns) For RAM , the time between presenting the address  and getting the valid data For non-RAM , discuss later  Transfer Rate Rate at which data can be moved  (K bps) For RAM ,  suppose 32 bits are read/written at a  time    (i.e. 1 memory cycle)  R=32 bits/memory cycle time (K bps)
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example If memory cycle is 250ns and 16 bits are read  each time, then the data transfer rate of the  memory is (
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chap5 - William Stallings Computer Organization and...

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