Chap12 - William Stallings Computer Organization and Architecture Chapter 12 CPU Structure and Function Structure The CPU CPU L y L y L h Computer

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William Stallings Computer Organization and Architecture Chapter 12 CPU Structure and Function
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Structure - The CPU Computer CPU I/O Memory System Bus Arithmetic and Login Unit Control Unit Internal CPU Interconnection Registers CPU Chapter 9 CPU L y L y , L h
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CPU With Systems Bus
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ALU Control Unit Internal CPU Interconnection Registers CPU CPU
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Registers && & & & & & & L $ ± ,  ł A ¶ “ *.  ł A ¶ “ CPU.  CPU must have some working space (temporary  storage) Called  register s Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy
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User Visible Registers General Purpose Data Address Condition Codes P443
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Example Register Organizations P419
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General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data data registers or accumulator Addressing segment register 
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General Purpose Registers (2) Make them general purpose Increase  flexibility  and programmer options Increase   instruction   size  & complexity Make them specialized Smaller (faster) instructions Less flexibility
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How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and  takes up processor  real estate See also RISC
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PowerPC User Visible Registers P451 RISC I
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How big? Large enough to hold full address Large enough to hold full word Often possible to combine two data registers C programming double  a; long int a;
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Condition Code Registers Sets of individual bits e.g. result of last operation was zero Can be read ( implicitly ) by programs e.g. JE --- Jump if zero Can not (usually) be set by programs May be  in  program status register P419
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P443
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Control & Status Registers P rogram  C ounter PC I nstruction Decoding  R egister IR M emory  A ddress  R egister MAR M emory  B uffer  R egister (MBR)   MDR Data
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Program Status Word A set of bits PSW: Includes Condition Codes Sign of last result Zero Carry Equal Overflow Control bits Interrupt enable/disable Supervisor P419~P443 PC flag
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Supervisor Mode Kernel mode Allows privileged instructions to execute Used by operating system Not available to user programs
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Other Registers May have registers pointing to: Process control blocks (see O/S) Interrupt Vectors (see O/S) N.B. CPU design and operating system design  are closely linked
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Foreground Reading Stallings Chapter 11 Manufacturer web sites & specs
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Instruction Cycle ( W & & ± – ² ¶ “ G ) Revision:  Stallings Chapter 3 P61
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Instruction Cycle ( x ¶ “ * ) 1. Fetch instructions 2. Interpret instructions 3. Calculate operand address 4.
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This note was uploaded on 03/31/2010 for the course SOFTWARE I c0327 taught by Professor Li during the Spring '09 term at Nanjing University.

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Chap12 - William Stallings Computer Organization and Architecture Chapter 12 CPU Structure and Function Structure The CPU CPU L y L y L h Computer

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